1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2254887a5SShengzhou Liu /* 3254887a5SShengzhou Liu * Copyright 2013 Freescale Semiconductor, Inc. 4254887a5SShengzhou Liu */ 5254887a5SShengzhou Liu 6254887a5SShengzhou Liu #ifndef __DDR_H__ 7254887a5SShengzhou Liu #define __DDR_H__ 8254887a5SShengzhou Liu struct board_specific_parameters { 9254887a5SShengzhou Liu u32 n_ranks; 10254887a5SShengzhou Liu u32 datarate_mhz_high; 11254887a5SShengzhou Liu u32 rank_gb; 12254887a5SShengzhou Liu u32 clk_adjust; 13254887a5SShengzhou Liu u32 wrlvl_start; 14254887a5SShengzhou Liu u32 wrlvl_ctl_2; 15254887a5SShengzhou Liu u32 wrlvl_ctl_3; 16254887a5SShengzhou Liu }; 17254887a5SShengzhou Liu 18254887a5SShengzhou Liu /* 19254887a5SShengzhou Liu * These tables contain all valid speeds we want to override with board 20254887a5SShengzhou Liu * specific parameters. datarate_mhz_high values need to be in ascending order 21254887a5SShengzhou Liu * for each n_ranks group. 22254887a5SShengzhou Liu */ 23254887a5SShengzhou Liu 24254887a5SShengzhou Liu static const struct board_specific_parameters udimm0[] = { 25254887a5SShengzhou Liu /* 26254887a5SShengzhou Liu * memory controller 0 27254887a5SShengzhou Liu * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | 28254887a5SShengzhou Liu * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | 29254887a5SShengzhou Liu */ 30e04f9d0cSShengzhou Liu {2, 1200, 0, 10, 7, 0x0708090a, 0x0b0c0d09}, 31e04f9d0cSShengzhou Liu {2, 1400, 0, 10, 7, 0x08090a0c, 0x0d0e0f0a}, 32e04f9d0cSShengzhou Liu {2, 1700, 0, 10, 8, 0x090a0b0c, 0x0e10110c}, 33e04f9d0cSShengzhou Liu {2, 1900, 0, 10, 8, 0x090b0c0f, 0x1012130d}, 34e04f9d0cSShengzhou Liu {2, 2140, 0, 10, 8, 0x090b0c0f, 0x1012130d}, 35e04f9d0cSShengzhou Liu {1, 1200, 0, 10, 7, 0x0808090a, 0x0b0c0c0a}, 36e04f9d0cSShengzhou Liu {1, 1500, 0, 10, 6, 0x07070809, 0x0a0b0b09}, 37e04f9d0cSShengzhou Liu {1, 1600, 0, 10, 8, 0x090b0b0d, 0x0d0e0f0b}, 38e04f9d0cSShengzhou Liu {1, 1700, 0, 8, 8, 0x080a0a0c, 0x0c0d0e0a}, 39e04f9d0cSShengzhou Liu {1, 1900, 0, 10, 8, 0x090a0c0d, 0x0e0f110c}, 40e04f9d0cSShengzhou Liu {1, 2140, 0, 8, 8, 0x090a0b0d, 0x0e0f110b}, 41254887a5SShengzhou Liu {} 42254887a5SShengzhou Liu }; 43254887a5SShengzhou Liu 44254887a5SShengzhou Liu static const struct board_specific_parameters rdimm0[] = { 45254887a5SShengzhou Liu /* 46254887a5SShengzhou Liu * memory controller 0 47254887a5SShengzhou Liu * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | 48254887a5SShengzhou Liu * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | 49254887a5SShengzhou Liu */ 50254887a5SShengzhou Liu /* TODO: need tuning these parameters if RDIMM is used */ 51e04f9d0cSShengzhou Liu {4, 1350, 0, 10, 9, 0x08070605, 0x06070806}, 52e04f9d0cSShengzhou Liu {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906}, 53e04f9d0cSShengzhou Liu {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, 54e04f9d0cSShengzhou Liu {2, 1350, 0, 10, 9, 0x08070605, 0x06070806}, 55e04f9d0cSShengzhou Liu {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, 56e04f9d0cSShengzhou Liu {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, 57e04f9d0cSShengzhou Liu {1, 1350, 0, 10, 9, 0x08070605, 0x06070806}, 58e04f9d0cSShengzhou Liu {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, 59e04f9d0cSShengzhou Liu {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07}, 60254887a5SShengzhou Liu {} 61254887a5SShengzhou Liu }; 62254887a5SShengzhou Liu 63254887a5SShengzhou Liu static const struct board_specific_parameters *udimms[] = { 64254887a5SShengzhou Liu udimm0, 65254887a5SShengzhou Liu }; 66254887a5SShengzhou Liu 67254887a5SShengzhou Liu static const struct board_specific_parameters *rdimms[] = { 68254887a5SShengzhou Liu rdimm0, 69254887a5SShengzhou Liu }; 70254887a5SShengzhou Liu #endif 71