1*48c6f328SShengzhou Liu /* 2*48c6f328SShengzhou Liu * Copyright 2014 Freescale Semiconductor, Inc. 3*48c6f328SShengzhou Liu * 4*48c6f328SShengzhou Liu * SPDX-License-Identifier: GPL-2.0+ 5*48c6f328SShengzhou Liu */ 6*48c6f328SShengzhou Liu 7*48c6f328SShengzhou Liu #include <common.h> 8*48c6f328SShengzhou Liu #include <asm/mmu.h> 9*48c6f328SShengzhou Liu 10*48c6f328SShengzhou Liu struct fsl_e_tlb_entry tlb_table[] = { 11*48c6f328SShengzhou Liu /* TLB 0 - for temp stack in cache */ 12*48c6f328SShengzhou Liu SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 13*48c6f328SShengzhou Liu CONFIG_SYS_INIT_RAM_ADDR_PHYS, 14*48c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, 0, 15*48c6f328SShengzhou Liu 0, 0, BOOKE_PAGESZ_4K, 0), 16*48c6f328SShengzhou Liu SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 17*48c6f328SShengzhou Liu CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 18*48c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, 0, 19*48c6f328SShengzhou Liu 0, 0, BOOKE_PAGESZ_4K, 0), 20*48c6f328SShengzhou Liu SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 21*48c6f328SShengzhou Liu CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 22*48c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, 0, 23*48c6f328SShengzhou Liu 0, 0, BOOKE_PAGESZ_4K, 0), 24*48c6f328SShengzhou Liu SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 25*48c6f328SShengzhou Liu CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 26*48c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, 0, 27*48c6f328SShengzhou Liu 0, 0, BOOKE_PAGESZ_4K, 0), 28*48c6f328SShengzhou Liu 29*48c6f328SShengzhou Liu /* TLB 1 */ 30*48c6f328SShengzhou Liu /* *I*** - Covers boot page */ 31*48c6f328SShengzhou Liu #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 32*48c6f328SShengzhou Liu /* 33*48c6f328SShengzhou Liu * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the 34*48c6f328SShengzhou Liu * SRAM is at 0xfffc0000, it covered the 0xfffff000. 35*48c6f328SShengzhou Liu */ 36*48c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 37*48c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 38*48c6f328SShengzhou Liu 0, 0, BOOKE_PAGESZ_256K, 1), 39*48c6f328SShengzhou Liu #else 40*48c6f328SShengzhou Liu SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 41*48c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 42*48c6f328SShengzhou Liu 0, 0, BOOKE_PAGESZ_4K, 1), 43*48c6f328SShengzhou Liu #endif 44*48c6f328SShengzhou Liu 45*48c6f328SShengzhou Liu /* *I*G* - CCSRBAR */ 46*48c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 47*48c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 48*48c6f328SShengzhou Liu 0, 1, BOOKE_PAGESZ_16M, 1), 49*48c6f328SShengzhou Liu 50*48c6f328SShengzhou Liu /* *I*G* - Flash, localbus */ 51*48c6f328SShengzhou Liu /* This will be changed to *I*G* after relocation to RAM. */ 52*48c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 53*48c6f328SShengzhou Liu MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 54*48c6f328SShengzhou Liu 0, 2, BOOKE_PAGESZ_256M, 1), 55*48c6f328SShengzhou Liu 56*48c6f328SShengzhou Liu #ifndef CONFIG_SPL_BUILD 57*48c6f328SShengzhou Liu /* *I*G* - PCI */ 58*48c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 59*48c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 60*48c6f328SShengzhou Liu 0, 3, BOOKE_PAGESZ_1G, 1), 61*48c6f328SShengzhou Liu 62*48c6f328SShengzhou Liu /* *I*G* - PCI I/O */ 63*48c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 64*48c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 65*48c6f328SShengzhou Liu 0, 4, BOOKE_PAGESZ_256K, 1), 66*48c6f328SShengzhou Liu 67*48c6f328SShengzhou Liu /* Bman/Qman */ 68*48c6f328SShengzhou Liu #ifdef CONFIG_SYS_BMAN_MEM_PHYS 69*48c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 70*48c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, 0, 71*48c6f328SShengzhou Liu 0, 5, BOOKE_PAGESZ_16M, 1), 72*48c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, 73*48c6f328SShengzhou Liu CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, 74*48c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 75*48c6f328SShengzhou Liu 0, 6, BOOKE_PAGESZ_16M, 1), 76*48c6f328SShengzhou Liu #endif 77*48c6f328SShengzhou Liu #ifdef CONFIG_SYS_QMAN_MEM_PHYS 78*48c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 79*48c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, 0, 80*48c6f328SShengzhou Liu 0, 7, BOOKE_PAGESZ_16M, 1), 81*48c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, 82*48c6f328SShengzhou Liu CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, 83*48c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 84*48c6f328SShengzhou Liu 0, 8, BOOKE_PAGESZ_16M, 1), 85*48c6f328SShengzhou Liu #endif 86*48c6f328SShengzhou Liu #endif 87*48c6f328SShengzhou Liu #ifdef CONFIG_SYS_DCSRBAR_PHYS 88*48c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 89*48c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 90*48c6f328SShengzhou Liu 0, 9, BOOKE_PAGESZ_4M, 1), 91*48c6f328SShengzhou Liu #endif 92*48c6f328SShengzhou Liu #ifdef CONFIG_SYS_NAND_BASE 93*48c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 94*48c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 95*48c6f328SShengzhou Liu 0, 10, BOOKE_PAGESZ_64K, 1), 96*48c6f328SShengzhou Liu #endif 97*48c6f328SShengzhou Liu #ifdef CONFIG_SYS_CPLD_BASE 98*48c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, 99*48c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 100*48c6f328SShengzhou Liu 0, 11, BOOKE_PAGESZ_256K, 1), 101*48c6f328SShengzhou Liu #endif 102*48c6f328SShengzhou Liu 103*48c6f328SShengzhou Liu #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) 104*48c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 105*48c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, 0, 106*48c6f328SShengzhou Liu 0, 12, BOOKE_PAGESZ_1G, 1), 107*48c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, 108*48c6f328SShengzhou Liu CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, 109*48c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, 0, 110*48c6f328SShengzhou Liu 0, 13, BOOKE_PAGESZ_1G, 1) 111*48c6f328SShengzhou Liu #endif 112*48c6f328SShengzhou Liu /* entry 14 and 15 has been used hard coded, they will be disabled 113*48c6f328SShengzhou Liu * in cpu_init_f, so if needed more, will use entry 16 later. 114*48c6f328SShengzhou Liu */ 115*48c6f328SShengzhou Liu }; 116*48c6f328SShengzhou Liu 117*48c6f328SShengzhou Liu int num_tlb_entries = ARRAY_SIZE(tlb_table); 118