148c6f328SShengzhou Liu /* 248c6f328SShengzhou Liu * Copyright 2014 Freescale Semiconductor, Inc. 348c6f328SShengzhou Liu * 448c6f328SShengzhou Liu * SPDX-License-Identifier: GPL-2.0+ 548c6f328SShengzhou Liu */ 648c6f328SShengzhou Liu 748c6f328SShengzhou Liu #include <common.h> 848c6f328SShengzhou Liu #include <asm/mmu.h> 948c6f328SShengzhou Liu 1048c6f328SShengzhou Liu struct fsl_e_tlb_entry tlb_table[] = { 1148c6f328SShengzhou Liu /* TLB 0 - for temp stack in cache */ 1248c6f328SShengzhou Liu SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 1348c6f328SShengzhou Liu CONFIG_SYS_INIT_RAM_ADDR_PHYS, 1448c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, 0, 1548c6f328SShengzhou Liu 0, 0, BOOKE_PAGESZ_4K, 0), 1648c6f328SShengzhou Liu SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 1748c6f328SShengzhou Liu CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 1848c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, 0, 1948c6f328SShengzhou Liu 0, 0, BOOKE_PAGESZ_4K, 0), 2048c6f328SShengzhou Liu SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 2148c6f328SShengzhou Liu CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 2248c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, 0, 2348c6f328SShengzhou Liu 0, 0, BOOKE_PAGESZ_4K, 0), 2448c6f328SShengzhou Liu SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 2548c6f328SShengzhou Liu CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 2648c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, 0, 2748c6f328SShengzhou Liu 0, 0, BOOKE_PAGESZ_4K, 0), 2848c6f328SShengzhou Liu 2948c6f328SShengzhou Liu /* TLB 1 */ 3048c6f328SShengzhou Liu /* *I*** - Covers boot page */ 3148c6f328SShengzhou Liu #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 3248c6f328SShengzhou Liu /* 3348c6f328SShengzhou Liu * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the 3448c6f328SShengzhou Liu * SRAM is at 0xfffc0000, it covered the 0xfffff000. 3548c6f328SShengzhou Liu */ 3648c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 3748c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 3848c6f328SShengzhou Liu 0, 0, BOOKE_PAGESZ_256K, 1), 3948c6f328SShengzhou Liu #else 4048c6f328SShengzhou Liu SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 4148c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 4248c6f328SShengzhou Liu 0, 0, BOOKE_PAGESZ_4K, 1), 4348c6f328SShengzhou Liu #endif 4448c6f328SShengzhou Liu 4548c6f328SShengzhou Liu /* *I*G* - CCSRBAR */ 4648c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 4748c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 4848c6f328SShengzhou Liu 0, 1, BOOKE_PAGESZ_16M, 1), 4948c6f328SShengzhou Liu 5048c6f328SShengzhou Liu /* *I*G* - Flash, localbus */ 5148c6f328SShengzhou Liu /* This will be changed to *I*G* after relocation to RAM. */ 5248c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 5348c6f328SShengzhou Liu MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 5448c6f328SShengzhou Liu 0, 2, BOOKE_PAGESZ_256M, 1), 5548c6f328SShengzhou Liu 5648c6f328SShengzhou Liu #ifndef CONFIG_SPL_BUILD 5748c6f328SShengzhou Liu /* *I*G* - PCI */ 5848c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 5948c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 6048c6f328SShengzhou Liu 0, 3, BOOKE_PAGESZ_1G, 1), 6148c6f328SShengzhou Liu 6248c6f328SShengzhou Liu /* *I*G* - PCI I/O */ 6348c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 6448c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 6548c6f328SShengzhou Liu 0, 4, BOOKE_PAGESZ_256K, 1), 6648c6f328SShengzhou Liu 6748c6f328SShengzhou Liu /* Bman/Qman */ 6848c6f328SShengzhou Liu #ifdef CONFIG_SYS_BMAN_MEM_PHYS 6948c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 7048c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, 0, 7148c6f328SShengzhou Liu 0, 5, BOOKE_PAGESZ_16M, 1), 7248c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, 7348c6f328SShengzhou Liu CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, 7448c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 7548c6f328SShengzhou Liu 0, 6, BOOKE_PAGESZ_16M, 1), 7648c6f328SShengzhou Liu #endif 7748c6f328SShengzhou Liu #ifdef CONFIG_SYS_QMAN_MEM_PHYS 7848c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 7948c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, 0, 8048c6f328SShengzhou Liu 0, 7, BOOKE_PAGESZ_16M, 1), 8148c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, 8248c6f328SShengzhou Liu CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, 8348c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 8448c6f328SShengzhou Liu 0, 8, BOOKE_PAGESZ_16M, 1), 8548c6f328SShengzhou Liu #endif 8648c6f328SShengzhou Liu #endif 8748c6f328SShengzhou Liu #ifdef CONFIG_SYS_DCSRBAR_PHYS 8848c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 8948c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 9048c6f328SShengzhou Liu 0, 9, BOOKE_PAGESZ_4M, 1), 9148c6f328SShengzhou Liu #endif 9248c6f328SShengzhou Liu #ifdef CONFIG_SYS_NAND_BASE 9348c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 9448c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 9548c6f328SShengzhou Liu 0, 10, BOOKE_PAGESZ_64K, 1), 9648c6f328SShengzhou Liu #endif 9748c6f328SShengzhou Liu #ifdef CONFIG_SYS_CPLD_BASE 9848c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, 9948c6f328SShengzhou Liu MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 10048c6f328SShengzhou Liu 0, 11, BOOKE_PAGESZ_256K, 1), 10148c6f328SShengzhou Liu #endif 10248c6f328SShengzhou Liu 10348c6f328SShengzhou Liu #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) 10448c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 105*316f0d0fSYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 10648c6f328SShengzhou Liu 0, 12, BOOKE_PAGESZ_1G, 1), 10748c6f328SShengzhou Liu SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, 10848c6f328SShengzhou Liu CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, 109*316f0d0fSYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 11048c6f328SShengzhou Liu 0, 13, BOOKE_PAGESZ_1G, 1) 11148c6f328SShengzhou Liu #endif 11248c6f328SShengzhou Liu /* entry 14 and 15 has been used hard coded, they will be disabled 11348c6f328SShengzhou Liu * in cpu_init_f, so if needed more, will use entry 16 later. 11448c6f328SShengzhou Liu */ 11548c6f328SShengzhou Liu }; 11648c6f328SShengzhou Liu 11748c6f328SShengzhou Liu int num_tlb_entries = ARRAY_SIZE(tlb_table); 118