1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the Free 8 * Software Foundation; either version 2 of the License, or (at your option) 9 * any later version. 10 */ 11 12 #include <common.h> 13 #include <command.h> 14 #include <pci.h> 15 #include <asm/processor.h> 16 #include <asm/mmu.h> 17 #include <asm/cache.h> 18 #include <asm/immap_85xx.h> 19 #include <asm/fsl_pci.h> 20 #include <asm/fsl_ddr_sdram.h> 21 #include <asm/fsl_serdes.h> 22 #include <asm/io.h> 23 #include <libfdt.h> 24 #include <fdt_support.h> 25 #include <tsec.h> 26 #include <asm/fsl_law.h> 27 #include <netdev.h> 28 #include <i2c.h> 29 #include <hwconfig.h> 30 31 #include "../common/ngpixis.h" 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 int board_early_init_f(void) 36 { 37 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 38 39 /* Set pmuxcr to allow both i2c1 and i2c2 */ 40 setbits_be32(&gur->pmuxcr, 0x1000); 41 42 /* Read back the register to synchronize the write. */ 43 in_be32(&gur->pmuxcr); 44 45 /* Set the pin muxing to enable ETSEC2. */ 46 clrbits_be32(&gur->pmuxcr2, 0x001F8000); 47 48 return 0; 49 } 50 51 int checkboard(void) 52 { 53 u8 sw; 54 55 puts("Board: P1022DS "); 56 57 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 58 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); 59 60 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); 61 62 switch ((sw & PIXIS_LBMAP_MASK) >> 6) { 63 case 0: 64 printf ("vBank: %u\n", ((sw & 0x30) >> 4)); 65 break; 66 case 1: 67 printf ("NAND\n"); 68 break; 69 case 2: 70 case 3: 71 puts ("Promjet\n"); 72 break; 73 } 74 75 return 0; 76 } 77 78 #define CONFIG_TFP410_I2C_ADDR 0x38 79 80 /* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */ 81 #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c 82 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03 83 84 /* Route the I2C1 pins to the SSI port instead. */ 85 #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08 86 87 /* Choose the 12.288Mhz codec reference clock */ 88 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02 89 90 /* Choose the 11.2896Mhz codec reference clock */ 91 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01 92 93 int misc_init_r(void) 94 { 95 u8 temp; 96 const char *audclk; 97 size_t arglen; 98 99 /* For DVI, enable the TFP410 Encoder. */ 100 101 temp = 0xBF; 102 if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) 103 return -1; 104 if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) 105 return -1; 106 debug("DVI Encoder Read: 0x%02x\n", temp); 107 108 temp = 0x10; 109 if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) 110 return -1; 111 if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) 112 return -1; 113 debug("DVI Encoder Read: 0x%02x\n",temp); 114 115 /* 116 * Enable the reference clock for the WM8776 codec, and route the MUX 117 * pins for SSI. The default is the 12.288 MHz clock 118 */ 119 120 temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK | 121 CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK); 122 temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI; 123 124 audclk = hwconfig_arg("audclk", &arglen); 125 /* Check the first two chars only */ 126 if (audclk && (strncmp(audclk, "11", 2) == 0)) 127 temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11; 128 else 129 temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12; 130 out_8(&pixis->brdcfg1, temp); 131 132 return 0; 133 } 134 135 /* 136 * A list of PCI and SATA slots 137 */ 138 enum slot_id { 139 SLOT_PCIE1 = 1, 140 SLOT_PCIE2, 141 SLOT_PCIE3, 142 SLOT_PCIE4, 143 SLOT_PCIE5, 144 SLOT_SATA1, 145 SLOT_SATA2 146 }; 147 148 /* 149 * This array maps the slot identifiers to their names on the P1022DS board. 150 */ 151 static const char *slot_names[] = { 152 [SLOT_PCIE1] = "Slot 1", 153 [SLOT_PCIE2] = "Slot 2", 154 [SLOT_PCIE3] = "Slot 3", 155 [SLOT_PCIE4] = "Slot 4", 156 [SLOT_PCIE5] = "Mini-PCIe", 157 [SLOT_SATA1] = "SATA 1", 158 [SLOT_SATA2] = "SATA 2", 159 }; 160 161 /* 162 * This array maps a given SERDES configuration and SERDES device to the PCI or 163 * SATA slot that it connects to. This mapping is hard-coded in the FPGA. 164 */ 165 static u8 serdes_dev_slot[][SATA2 + 1] = { 166 [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 }, 167 [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 168 [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4, 169 [PCIE2] = SLOT_PCIE5 }, 170 [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2, 171 [PCIE2] = SLOT_PCIE3, 172 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 173 [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2, 174 [PCIE2] = SLOT_PCIE3 }, 175 [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3, 176 [PCIE2] = SLOT_PCIE3, 177 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 178 [0x1c] = { [PCIE1] = SLOT_PCIE1, 179 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 180 [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 }, 181 [0x1f] = { [PCIE1] = SLOT_PCIE1 }, 182 }; 183 184 185 /* 186 * Returns the name of the slot to which the PCIe or SATA controller is 187 * connected 188 */ 189 const char *board_serdes_name(enum srds_prtcl device) 190 { 191 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 192 u32 pordevsr = in_be32(&gur->pordevsr); 193 unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 194 MPC85xx_PORDEVSR_IO_SEL_SHIFT; 195 enum slot_id slot = serdes_dev_slot[srds_cfg][device]; 196 const char *name = slot_names[slot]; 197 198 if (name) 199 return name; 200 else 201 return "Nothing"; 202 } 203 204 #ifdef CONFIG_PCI 205 void pci_init_board(void) 206 { 207 fsl_pcie_init_board(0); 208 } 209 #endif 210 211 int board_early_init_r(void) 212 { 213 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 214 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 215 216 /* 217 * Remap Boot flash + PROMJET region to caching-inhibited 218 * so that flash can be erased properly. 219 */ 220 221 /* Flush d-cache and invalidate i-cache of any FLASH data */ 222 flush_dcache(); 223 invalidate_icache(); 224 225 /* invalidate existing TLB entry for flash + promjet */ 226 disable_tlb(flash_esel); 227 228 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 229 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 230 0, flash_esel, BOOKE_PAGESZ_256M, 1); 231 232 return 0; 233 } 234 235 /* 236 * Initialize on-board and/or PCI Ethernet devices 237 * 238 * Returns: 239 * <0, error 240 * 0, no ethernet devices found 241 * >0, number of ethernet devices initialized 242 */ 243 int board_eth_init(bd_t *bis) 244 { 245 struct tsec_info_struct tsec_info[2]; 246 unsigned int num = 0; 247 248 #ifdef CONFIG_TSEC1 249 SET_STD_TSEC_INFO(tsec_info[num], 1); 250 num++; 251 #endif 252 #ifdef CONFIG_TSEC2 253 SET_STD_TSEC_INFO(tsec_info[num], 2); 254 num++; 255 #endif 256 257 return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis); 258 } 259 260 #ifdef CONFIG_OF_BOARD_SETUP 261 /** 262 * ft_codec_setup - fix up the clock-frequency property of the codec node 263 * 264 * Update the clock-frequency property based on the value of the 'audclk' 265 * hwconfig option. If audclk is not specified, then default to 12.288MHz. 266 */ 267 static void ft_codec_setup(void *blob, const char *compatible) 268 { 269 const char *audclk; 270 size_t arglen; 271 u32 freq; 272 273 audclk = hwconfig_arg("audclk", &arglen); 274 if (audclk && (strncmp(audclk, "11", 2) == 0)) 275 freq = 11289600; 276 else 277 freq = 12288000; 278 279 do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1); 280 } 281 282 void ft_board_setup(void *blob, bd_t *bd) 283 { 284 phys_addr_t base; 285 phys_size_t size; 286 287 ft_cpu_setup(blob, bd); 288 289 base = getenv_bootm_low(); 290 size = getenv_bootm_size(); 291 292 fdt_fixup_memory(blob, (u64)base, (u64)size); 293 294 FT_FSL_PCI_SETUP; 295 296 #ifdef CONFIG_FSL_SGMII_RISER 297 fsl_sgmii_riser_fdt_fixup(blob); 298 #endif 299 300 /* Update the WM8776 node's clock frequency property */ 301 ft_codec_setup(blob, "wlf,wm8776"); 302 } 303 #endif 304