1 /* 2 * Copyright 2010 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the Free 8 * Software Foundation; either version 2 of the License, or (at your option) 9 * any later version. 10 */ 11 12 #include <common.h> 13 #include <command.h> 14 #include <pci.h> 15 #include <asm/processor.h> 16 #include <asm/mmu.h> 17 #include <asm/cache.h> 18 #include <asm/immap_85xx.h> 19 #include <asm/fsl_pci.h> 20 #include <asm/fsl_ddr_sdram.h> 21 #include <asm/fsl_serdes.h> 22 #include <asm/io.h> 23 #include <libfdt.h> 24 #include <fdt_support.h> 25 #include <tsec.h> 26 #include <asm/fsl_law.h> 27 #include <asm/mp.h> 28 #include <netdev.h> 29 #include <i2c.h> 30 #include <hwconfig.h> 31 32 #include "../common/ngpixis.h" 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 int board_early_init_f(void) 37 { 38 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 39 40 /* Set pmuxcr to allow both i2c1 and i2c2 */ 41 setbits_be32(&gur->pmuxcr, 0x1000); 42 43 /* Read back the register to synchronize the write. */ 44 in_be32(&gur->pmuxcr); 45 46 /* Set the pin muxing to enable ETSEC2. */ 47 clrbits_be32(&gur->pmuxcr2, 0x001F8000); 48 49 return 0; 50 } 51 52 int checkboard(void) 53 { 54 u8 sw; 55 56 puts("Board: P1022DS "); 57 58 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 59 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); 60 61 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); 62 63 switch ((sw & PIXIS_LBMAP_MASK) >> 6) { 64 case 0: 65 printf ("vBank: %u\n", ((sw & 0x30) >> 4)); 66 break; 67 case 1: 68 printf ("NAND\n"); 69 break; 70 case 2: 71 case 3: 72 puts ("Promjet\n"); 73 break; 74 } 75 76 return 0; 77 } 78 79 #define CONFIG_TFP410_I2C_ADDR 0x38 80 81 /* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */ 82 #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c 83 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03 84 85 /* Route the I2C1 pins to the SSI port instead. */ 86 #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08 87 88 /* Choose the 12.288Mhz codec reference clock */ 89 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02 90 91 /* Choose the 11.2896Mhz codec reference clock */ 92 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01 93 94 int misc_init_r(void) 95 { 96 u8 temp; 97 const char *audclk; 98 size_t arglen; 99 100 /* For DVI, enable the TFP410 Encoder. */ 101 102 temp = 0xBF; 103 if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) 104 return -1; 105 if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) 106 return -1; 107 debug("DVI Encoder Read: 0x%02x\n", temp); 108 109 temp = 0x10; 110 if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) 111 return -1; 112 if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) 113 return -1; 114 debug("DVI Encoder Read: 0x%02x\n",temp); 115 116 /* 117 * Enable the reference clock for the WM8776 codec, and route the MUX 118 * pins for SSI. The default is the 12.288 MHz clock 119 */ 120 121 temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK | 122 CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK); 123 temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI; 124 125 audclk = hwconfig_arg("audclk", &arglen); 126 /* Check the first two chars only */ 127 if (audclk && (strncmp(audclk, "11", 2) == 0)) 128 temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11; 129 else 130 temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12; 131 out_8(&pixis->brdcfg1, temp); 132 133 return 0; 134 } 135 136 /* 137 * A list of PCI and SATA slots 138 */ 139 enum slot_id { 140 SLOT_PCIE1 = 1, 141 SLOT_PCIE2, 142 SLOT_PCIE3, 143 SLOT_PCIE4, 144 SLOT_PCIE5, 145 SLOT_SATA1, 146 SLOT_SATA2 147 }; 148 149 /* 150 * This array maps the slot identifiers to their names on the P1022DS board. 151 */ 152 static const char *slot_names[] = { 153 [SLOT_PCIE1] = "Slot 1", 154 [SLOT_PCIE2] = "Slot 2", 155 [SLOT_PCIE3] = "Slot 3", 156 [SLOT_PCIE4] = "Slot 4", 157 [SLOT_PCIE5] = "Mini-PCIe", 158 [SLOT_SATA1] = "SATA 1", 159 [SLOT_SATA2] = "SATA 2", 160 }; 161 162 /* 163 * This array maps a given SERDES configuration and SERDES device to the PCI or 164 * SATA slot that it connects to. This mapping is hard-coded in the FPGA. 165 */ 166 static u8 serdes_dev_slot[][SATA2 + 1] = { 167 [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 }, 168 [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 169 [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4, 170 [PCIE2] = SLOT_PCIE5 }, 171 [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2, 172 [PCIE2] = SLOT_PCIE3, 173 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 174 [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2, 175 [PCIE2] = SLOT_PCIE3 }, 176 [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3, 177 [PCIE2] = SLOT_PCIE3, 178 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 179 [0x1c] = { [PCIE1] = SLOT_PCIE1, 180 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 181 [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 }, 182 [0x1f] = { [PCIE1] = SLOT_PCIE1 }, 183 }; 184 185 186 /* 187 * Returns the name of the slot to which the PCIe or SATA controller is 188 * connected 189 */ 190 const char *serdes_slot_name(enum srds_prtcl device) 191 { 192 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 193 u32 pordevsr = in_be32(&gur->pordevsr); 194 unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 195 MPC85xx_PORDEVSR_IO_SEL_SHIFT; 196 enum slot_id slot = serdes_dev_slot[srds_cfg][device]; 197 const char *name = slot_names[slot]; 198 199 if (name) 200 return name; 201 else 202 return "Nothing"; 203 } 204 205 static void configure_pcie(struct fsl_pci_info *info, 206 struct pci_controller *hose, 207 const char *connected) 208 { 209 static int bus_number = 0; 210 int is_endpoint; 211 212 set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law); 213 set_next_law(info->io_phys, law_size_bits(info->io_size), info->law); 214 is_endpoint = fsl_setup_hose(hose, info->regs); 215 printf("PCIE%u: connected to %s as %s (base addr %lx)\n", 216 info->pci_num, connected, 217 is_endpoint ? "Endpoint" : "Root Complex", info->regs); 218 bus_number = fsl_pci_init_port(info, hose, bus_number); 219 } 220 221 #ifdef CONFIG_PCIE1 222 static struct pci_controller pcie1_hose; 223 #endif 224 225 #ifdef CONFIG_PCIE2 226 static struct pci_controller pcie2_hose; 227 #endif 228 229 #ifdef CONFIG_PCIE3 230 static struct pci_controller pcie3_hose; 231 #endif 232 233 #ifdef CONFIG_PCI 234 void pci_init_board(void) 235 { 236 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 237 struct fsl_pci_info pci_info; 238 u32 devdisr = in_be32(&gur->devdisr); 239 240 #ifdef CONFIG_PCIE1 241 if (is_serdes_configured(PCIE1) && !(devdisr & MPC85xx_DEVDISR_PCIE)) { 242 SET_STD_PCIE_INFO(pci_info, 1); 243 configure_pcie(&pci_info, &pcie1_hose, serdes_slot_name(PCIE1)); 244 } else { 245 printf("PCIE1: disabled\n"); 246 } 247 #else 248 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ 249 #endif 250 251 #ifdef CONFIG_PCIE2 252 if (is_serdes_configured(PCIE2) && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { 253 SET_STD_PCIE_INFO(pci_info, 2); 254 configure_pcie(&pci_info, &pcie2_hose, serdes_slot_name(PCIE2)); 255 } else { 256 printf("PCIE2: disabled\n"); 257 } 258 #else 259 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ 260 #endif 261 262 #ifdef CONFIG_PCIE3 263 if (is_serdes_configured(PCIE3) && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { 264 SET_STD_PCIE_INFO(pci_info, 3); 265 configure_pcie(&pci_info, &pcie3_hose, serdes_slot_name(PCIE3)); 266 } else { 267 printf("PCIE3: disabled\n"); 268 } 269 #else 270 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ 271 #endif 272 } 273 #endif 274 275 int board_early_init_r(void) 276 { 277 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 278 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 279 280 /* 281 * Remap Boot flash + PROMJET region to caching-inhibited 282 * so that flash can be erased properly. 283 */ 284 285 /* Flush d-cache and invalidate i-cache of any FLASH data */ 286 flush_dcache(); 287 invalidate_icache(); 288 289 /* invalidate existing TLB entry for flash + promjet */ 290 disable_tlb(flash_esel); 291 292 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 293 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 294 0, flash_esel, BOOKE_PAGESZ_256M, 1); 295 296 return 0; 297 } 298 299 /* 300 * Initialize on-board and/or PCI Ethernet devices 301 * 302 * Returns: 303 * <0, error 304 * 0, no ethernet devices found 305 * >0, number of ethernet devices initialized 306 */ 307 int board_eth_init(bd_t *bis) 308 { 309 struct tsec_info_struct tsec_info[2]; 310 unsigned int num = 0; 311 312 #ifdef CONFIG_TSEC1 313 SET_STD_TSEC_INFO(tsec_info[num], 1); 314 num++; 315 #endif 316 #ifdef CONFIG_TSEC2 317 SET_STD_TSEC_INFO(tsec_info[num], 2); 318 num++; 319 #endif 320 321 return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis); 322 } 323 324 #ifdef CONFIG_OF_BOARD_SETUP 325 /** 326 * ft_codec_setup - fix up the clock-frequency property of the codec node 327 * 328 * Update the clock-frequency property based on the value of the 'audclk' 329 * hwconfig option. If audclk is not specified, then default to 12.288MHz. 330 */ 331 static void ft_codec_setup(void *blob, const char *compatible) 332 { 333 const char *audclk; 334 size_t arglen; 335 u32 freq; 336 337 audclk = hwconfig_arg("audclk", &arglen); 338 if (audclk && (strncmp(audclk, "11", 2) == 0)) 339 freq = 11289600; 340 else 341 freq = 12288000; 342 343 do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1); 344 } 345 346 void ft_board_setup(void *blob, bd_t *bd) 347 { 348 phys_addr_t base; 349 phys_size_t size; 350 351 ft_cpu_setup(blob, bd); 352 353 base = getenv_bootm_low(); 354 size = getenv_bootm_size(); 355 356 fdt_fixup_memory(blob, (u64)base, (u64)size); 357 358 FT_FSL_PCI_SETUP; 359 360 #ifdef CONFIG_FSL_SGMII_RISER 361 fsl_sgmii_riser_fdt_fixup(blob); 362 #endif 363 364 /* Update the WM8776 node's clock frequency property */ 365 ft_codec_setup(blob, "wlf,wm8776"); 366 } 367 #endif 368 369 #ifdef CONFIG_MP 370 void board_lmb_reserve(struct lmb *lmb) 371 { 372 cpu_mp_lmb_reserve(lmb); 373 } 374 #endif 375