1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * Authors: Timur Tabi <timur@freescale.com> 4 * 5 * FSL DIU Framebuffer driver 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the Free 9 * Software Foundation; either version 2 of the License, or (at your option) 10 * any later version. 11 */ 12 13 #include <common.h> 14 #include <command.h> 15 #include <asm/io.h> 16 #include <stdio_dev.h> 17 #include <video_fb.h> 18 #include "../common/ngpixis.h" 19 #include <fsl_diu_fb.h> 20 21 /* The CTL register is called 'csr' in the ngpixis_t structure */ 22 #define PX_CTL_ALTACC 0x80 23 24 #define PX_BRDCFG0_ELBC_SPI_MASK 0xc0 25 #define PX_BRDCFG0_ELBC_SPI_ELBC 0x00 26 #define PX_BRDCFG0_ELBC_SPI_NULL 0xc0 27 #define PX_BRDCFG0_ELBC_DIU 0x02 28 29 #define PX_BRDCFG1_DVIEN 0x80 30 #define PX_BRDCFG1_DFPEN 0x40 31 #define PX_BRDCFG1_BACKLIGHT 0x20 32 33 #define PMUXCR_ELBCDIU_MASK 0xc0000000 34 #define PMUXCR_ELBCDIU_NOR16 0x80000000 35 #define PMUXCR_ELBCDIU_DIU 0x40000000 36 37 /* 38 * DIU Area Descriptor 39 * 40 * Note that we need to byte-swap the value before it's written to the AD 41 * register. So even though the registers don't look like they're in the same 42 * bit positions as they are on the MPC8610, the same value is written to the 43 * AD register on the MPC8610 and on the P1022. 44 */ 45 #define AD_BYTE_F 0x10000000 46 #define AD_ALPHA_C_SHIFT 25 47 #define AD_BLUE_C_SHIFT 23 48 #define AD_GREEN_C_SHIFT 21 49 #define AD_RED_C_SHIFT 19 50 #define AD_PIXEL_S_SHIFT 16 51 #define AD_COMP_3_SHIFT 12 52 #define AD_COMP_2_SHIFT 8 53 #define AD_COMP_1_SHIFT 4 54 #define AD_COMP_0_SHIFT 0 55 56 /* 57 * Variables used by the DIU/LBC switching code. It's safe to makes these 58 * global, because the DIU requires DDR, so we'll only run this code after 59 * relocation. 60 */ 61 static u8 px_brdcfg0; 62 static u32 pmuxcr; 63 static void *lbc_lcs0_ba; 64 static void *lbc_lcs1_ba; 65 66 void diu_set_pixel_clock(unsigned int pixclock) 67 { 68 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 69 unsigned long speed_ccb, temp; 70 u32 pixval; 71 72 speed_ccb = get_bus_freq(0); 73 temp = 1000000000 / pixclock; 74 temp *= 1000; 75 pixval = speed_ccb / temp; 76 debug("DIU pixval = %lu\n", pixval); 77 78 /* Modify PXCLK in GUTS CLKDVDR */ 79 temp = in_be32(&gur->clkdvdr) & 0x2000FFFF; 80 out_be32(&gur->clkdvdr, temp); /* turn off clock */ 81 out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16)); 82 } 83 84 int platform_diu_init(unsigned int *xres, unsigned int *yres) 85 { 86 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 87 char *monitor_port; 88 u32 pixel_format; 89 u8 temp; 90 91 /* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */ 92 lbc_lcs0_ba = (void *)(get_lbc_br(0) & get_lbc_or(0) & 0xFFFF8000); 93 lbc_lcs1_ba = (void *)(get_lbc_br(1) & get_lbc_or(1) & 0xFFFF8000); 94 95 pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) | 96 (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) | 97 (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) | 98 (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) | 99 (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT)); 100 101 temp = in_8(&pixis->brdcfg1); 102 103 monitor_port = getenv("monitor"); 104 if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */ 105 *xres = 1024; 106 *yres = 768; 107 /* Enable the DFP port, disable the DVI and the backlight */ 108 temp &= ~(PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT); 109 temp |= PX_BRDCFG1_DFPEN; 110 } else { /* DVI */ 111 *xres = 1280; 112 *yres = 1024; 113 /* Enable the DVI port, disable the DFP and the backlight */ 114 temp &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT); 115 temp |= PX_BRDCFG1_DVIEN; 116 } 117 118 out_8(&pixis->brdcfg1, temp); 119 120 /* 121 * Enable PIXIS indirect access mode. This is a hack that allows us to 122 * access PIXIS registers even when the LBC pins have been muxed to the 123 * DIU. 124 */ 125 setbits_8(&pixis->csr, PX_CTL_ALTACC); 126 127 /* 128 * Route the LAD pins to the DIU. This will disable access to the eLBC, 129 * which means we won't be able to read/write any NOR flash addresses! 130 */ 131 out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0)); 132 px_brdcfg0 = in_8(lbc_lcs1_ba); 133 out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU); 134 135 /* Set PMUXCR to switch the muxed pins from the LBC to the DIU */ 136 clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU); 137 pmuxcr = in_be32(&gur->pmuxcr); 138 139 return fsl_diu_init(*xres, pixel_format, 0); 140 } 141 142 /* 143 * set_mux_to_lbc - disable the DIU so that we can read/write to elbc 144 * 145 * On the Freescale P1022, the DIU video signal and the LBC address/data lines 146 * share the same pins, which means that when the DIU is active (e.g. the 147 * console is on the DVI display), NOR flash cannot be accessed. So we use the 148 * weak accessor feature of the CFI flash code to temporarily switch the pin 149 * mux from DIU to LBC whenever we want to read or write flash. This has a 150 * significant performance penalty, but it's the only way to make it work. 151 * 152 * There are two muxes: one on the chip, and one on the board. The chip mux 153 * controls whether the pins are used for the DIU or the LBC, and it is 154 * set via PMUXCR. The board mux controls whether those signals go to 155 * the video connector or the NOR flash chips, and it is set via the ngPIXIS. 156 */ 157 static int set_mux_to_lbc(void) 158 { 159 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 160 161 /* Switch the muxes only if they're currently set to DIU mode */ 162 if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) != 163 PMUXCR_ELBCDIU_NOR16) { 164 /* 165 * In DIU mode, the PIXIS can only be accessed indirectly 166 * since we can't read/write the LBC directly. 167 */ 168 169 /* Set the board mux to LBC. This will disable the display. */ 170 out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0)); 171 px_brdcfg0 = in_8(lbc_lcs1_ba); 172 out_8(lbc_lcs1_ba, (px_brdcfg0 & ~(PX_BRDCFG0_ELBC_SPI_MASK 173 | PX_BRDCFG0_ELBC_DIU)) | PX_BRDCFG0_ELBC_SPI_ELBC); 174 175 /* Disable indirect PIXIS mode */ 176 out_8(lbc_lcs0_ba, offsetof(ngpixis_t, csr)); 177 clrbits_8(lbc_lcs1_ba, PX_CTL_ALTACC); 178 179 /* Set the chip mux to LBC mode, so that writes go to flash. */ 180 out_be32(&gur->pmuxcr, (pmuxcr & ~PMUXCR_ELBCDIU_MASK) | 181 PMUXCR_ELBCDIU_NOR16); 182 in_be32(&gur->pmuxcr); 183 184 return 1; 185 } 186 187 return 0; 188 } 189 190 /* 191 * set_mux_to_diu - re-enable the DIU muxing 192 * 193 * This function restores the chip and board muxing to point to the DIU. 194 */ 195 static void set_mux_to_diu(void) 196 { 197 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 198 199 /* Enable indirect PIXIS mode */ 200 setbits_8(&pixis->csr, PX_CTL_ALTACC); 201 202 /* Set the board mux to DIU. This will enable the display. */ 203 out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0)); 204 out_8(lbc_lcs1_ba, px_brdcfg0); 205 in_8(lbc_lcs1_ba); 206 207 /* Set the chip mux to DIU mode. */ 208 out_be32(&gur->pmuxcr, pmuxcr); 209 in_be32(&gur->pmuxcr); 210 } 211 212 /* 213 * pixis_read - board-specific function to read from the PIXIS 214 * 215 * This function overrides the generic pixis_read() function, so that it can 216 * use PIXIS indirect mode if necessary. 217 */ 218 u8 pixis_read(unsigned int reg) 219 { 220 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 221 222 /* Use indirect mode if the mux is currently set to DIU mode */ 223 if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) != 224 PMUXCR_ELBCDIU_NOR16) { 225 out_8(lbc_lcs0_ba, reg); 226 return in_8(lbc_lcs1_ba); 227 } else { 228 void *p = (void *)PIXIS_BASE; 229 230 return in_8(p + reg); 231 } 232 } 233 234 /* 235 * pixis_write - board-specific function to write to the PIXIS 236 * 237 * This function overrides the generic pixis_write() function, so that it can 238 * use PIXIS indirect mode if necessary. 239 */ 240 void pixis_write(unsigned int reg, u8 value) 241 { 242 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 243 244 /* Use indirect mode if the mux is currently set to DIU mode */ 245 if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) != 246 PMUXCR_ELBCDIU_NOR16) { 247 out_8(lbc_lcs0_ba, reg); 248 out_8(lbc_lcs1_ba, value); 249 /* Do a read-back to ensure the write completed */ 250 in_8(lbc_lcs1_ba); 251 } else { 252 void *p = (void *)PIXIS_BASE; 253 254 out_8(p + reg, value); 255 } 256 } 257 258 void pixis_bank_reset(void) 259 { 260 /* 261 * For some reason, a PIXIS bank reset does not work if the PIXIS is 262 * in indirect mode, so switch to direct mode first. 263 */ 264 set_mux_to_lbc(); 265 266 out_8(&pixis->vctl, 0); 267 out_8(&pixis->vctl, 1); 268 269 while (1); 270 } 271 272 #ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 273 274 void flash_write8(u8 value, void *addr) 275 { 276 int sw = set_mux_to_lbc(); 277 278 __raw_writeb(value, addr); 279 if (sw) { 280 /* 281 * To ensure the post-write is completed to eLBC, software must 282 * perform a dummy read from one valid address from eLBC space 283 * before changing the eLBC_DIU from NOR mode to DIU mode. 284 * set_mux_to_diu() includes a sync that will ensure the 285 * __raw_readb() completes before it switches the mux. 286 */ 287 __raw_readb(addr); 288 set_mux_to_diu(); 289 } 290 } 291 292 void flash_write16(u16 value, void *addr) 293 { 294 int sw = set_mux_to_lbc(); 295 296 __raw_writew(value, addr); 297 if (sw) { 298 /* 299 * To ensure the post-write is completed to eLBC, software must 300 * perform a dummy read from one valid address from eLBC space 301 * before changing the eLBC_DIU from NOR mode to DIU mode. 302 * set_mux_to_diu() includes a sync that will ensure the 303 * __raw_readb() completes before it switches the mux. 304 */ 305 __raw_readb(addr); 306 set_mux_to_diu(); 307 } 308 } 309 310 void flash_write32(u32 value, void *addr) 311 { 312 int sw = set_mux_to_lbc(); 313 314 __raw_writel(value, addr); 315 if (sw) { 316 /* 317 * To ensure the post-write is completed to eLBC, software must 318 * perform a dummy read from one valid address from eLBC space 319 * before changing the eLBC_DIU from NOR mode to DIU mode. 320 * set_mux_to_diu() includes a sync that will ensure the 321 * __raw_readb() completes before it switches the mux. 322 */ 323 __raw_readb(addr); 324 set_mux_to_diu(); 325 } 326 } 327 328 void flash_write64(u64 value, void *addr) 329 { 330 int sw = set_mux_to_lbc(); 331 uint32_t *p = addr; 332 333 /* 334 * There is no __raw_writeq(), so do the write manually. We don't trust 335 * the compiler, so we use inline assembly. 336 */ 337 __asm__ __volatile__( 338 "stw%U0%X0 %2,%0;\n" 339 "stw%U1%X1 %3,%1;\n" 340 : "=m" (*p), "=m" (*(p + 1)) 341 : "r" ((uint32_t) (value >> 32)), "r" ((uint32_t) (value))); 342 343 if (sw) { 344 /* 345 * To ensure the post-write is completed to eLBC, software must 346 * perform a dummy read from one valid address from eLBC space 347 * before changing the eLBC_DIU from NOR mode to DIU mode. We 348 * read addr+4 because we just wrote to addr+4, so that's how we 349 * maintain execution order. set_mux_to_diu() includes a sync 350 * that will ensure the __raw_readb() completes before it 351 * switches the mux. 352 */ 353 __raw_readb(addr + 4); 354 set_mux_to_diu(); 355 } 356 } 357 358 u8 flash_read8(void *addr) 359 { 360 u8 ret; 361 362 int sw = set_mux_to_lbc(); 363 364 ret = __raw_readb(addr); 365 if (sw) 366 set_mux_to_diu(); 367 368 return ret; 369 } 370 371 u16 flash_read16(void *addr) 372 { 373 u16 ret; 374 375 int sw = set_mux_to_lbc(); 376 377 ret = __raw_readw(addr); 378 if (sw) 379 set_mux_to_diu(); 380 381 return ret; 382 } 383 384 u32 flash_read32(void *addr) 385 { 386 u32 ret; 387 388 int sw = set_mux_to_lbc(); 389 390 ret = __raw_readl(addr); 391 if (sw) 392 set_mux_to_diu(); 393 394 return ret; 395 } 396 397 u64 flash_read64(void *addr) 398 { 399 u64 ret; 400 401 int sw = set_mux_to_lbc(); 402 403 /* There is no __raw_readq(), so do the read manually */ 404 ret = *(volatile u64 *)addr; 405 if (sw) 406 set_mux_to_diu(); 407 408 return ret; 409 } 410 411 #endif 412