1 /* 2 * Copyright 2010 Freescale Semiconductor, Inc. 3 * Authors: Timur Tabi <timur@freescale.com> 4 * 5 * FSL DIU Framebuffer driver 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the Free 9 * Software Foundation; either version 2 of the License, or (at your option) 10 * any later version. 11 */ 12 13 #include <common.h> 14 #include <command.h> 15 #include <asm/io.h> 16 #include <stdio_dev.h> 17 #include <video_fb.h> 18 #include "../common/ngpixis.h" 19 #include <fsl_diu_fb.h> 20 21 /* The CTL register is called 'csr' in the ngpixis_t structure */ 22 #define PX_CTL_ALTACC 0x80 23 24 #define PX_BRDCFG0_ELBC_SPI_MASK 0xc0 25 #define PX_BRDCFG0_ELBC_SPI_ELBC 0x00 26 #define PX_BRDCFG0_ELBC_SPI_NULL 0xc0 27 #define PX_BRDCFG0_ELBC_DIU 0x02 28 29 #define PX_BRDCFG1_DVIEN 0x80 30 #define PX_BRDCFG1_DFPEN 0x40 31 #define PX_BRDCFG1_BACKLIGHT 0x20 32 33 #define PMUXCR_ELBCDIU_MASK 0xc0000000 34 #define PMUXCR_ELBCDIU_NOR16 0x80000000 35 #define PMUXCR_ELBCDIU_DIU 0x40000000 36 37 /* 38 * DIU Area Descriptor 39 * 40 * Note that we need to byte-swap the value before it's written to the AD 41 * register. So even though the registers don't look like they're in the same 42 * bit positions as they are on the MPC8610, the same value is written to the 43 * AD register on the MPC8610 and on the P1022. 44 */ 45 #define AD_BYTE_F 0x10000000 46 #define AD_ALPHA_C_SHIFT 25 47 #define AD_BLUE_C_SHIFT 23 48 #define AD_GREEN_C_SHIFT 21 49 #define AD_RED_C_SHIFT 19 50 #define AD_PIXEL_S_SHIFT 16 51 #define AD_COMP_3_SHIFT 12 52 #define AD_COMP_2_SHIFT 8 53 #define AD_COMP_1_SHIFT 4 54 #define AD_COMP_0_SHIFT 0 55 56 /* 57 * Variables used by the DIU/LBC switching code. It's safe to makes these 58 * global, because the DIU requires DDR, so we'll only run this code after 59 * relocation. 60 */ 61 static u8 px_brdcfg0; 62 static u32 pmuxcr; 63 static void *lbc_lcs0_ba; 64 static void *lbc_lcs1_ba; 65 66 void diu_set_pixel_clock(unsigned int pixclock) 67 { 68 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 69 unsigned long speed_ccb, temp; 70 u32 pixval; 71 72 speed_ccb = get_bus_freq(0); 73 temp = 1000000000 / pixclock; 74 temp *= 1000; 75 pixval = speed_ccb / temp; 76 debug("DIU pixval = %lu\n", pixval); 77 78 /* Modify PXCLK in GUTS CLKDVDR */ 79 temp = in_be32(&gur->clkdvdr) & 0x2000FFFF; 80 out_be32(&gur->clkdvdr, temp); /* turn off clock */ 81 out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16)); 82 } 83 84 int platform_diu_init(unsigned int *xres, unsigned int *yres) 85 { 86 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 87 char *monitor_port; 88 u32 pixel_format; 89 u8 temp; 90 91 /* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */ 92 lbc_lcs0_ba = (void *)(get_lbc_br(0) & get_lbc_or(0) & 0xFFFF8000); 93 lbc_lcs1_ba = (void *)(get_lbc_br(1) & get_lbc_or(1) & 0xFFFF8000); 94 95 pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) | 96 (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) | 97 (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) | 98 (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) | 99 (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT)); 100 101 temp = in_8(&pixis->brdcfg1); 102 103 monitor_port = getenv("monitor"); 104 if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */ 105 *xres = 1024; 106 *yres = 768; 107 /* Enable the DFP port, disable the DVI and the backlight */ 108 temp &= ~(PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT); 109 temp |= PX_BRDCFG1_DFPEN; 110 } else { /* DVI */ 111 *xres = 1280; 112 *yres = 1024; 113 /* Enable the DVI port, disable the DFP and the backlight */ 114 temp &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT); 115 temp |= PX_BRDCFG1_DVIEN; 116 } 117 118 out_8(&pixis->brdcfg1, temp); 119 120 /* 121 * Enable PIXIS indirect access mode. This is a hack that allows us to 122 * access PIXIS registers even when the LBC pins have been muxed to the 123 * DIU. 124 */ 125 setbits_8(&pixis->csr, PX_CTL_ALTACC); 126 127 /* 128 * Route the LAD pins to the DIU. This will disable access to the eLBC, 129 * which means we won't be able to read/write any NOR flash addresses! 130 */ 131 out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0)); 132 px_brdcfg0 = in_8(lbc_lcs1_ba); 133 out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU); 134 135 /* Set PMUXCR to switch the muxed pins from the LBC to the DIU */ 136 clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU); 137 pmuxcr = in_be32(&gur->pmuxcr); 138 139 return fsl_diu_init(*xres, pixel_format, 0); 140 } 141 142 #ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 143 144 /* 145 * set_mux_to_lbc - disable the DIU so that we can read/write to elbc 146 * 147 * On the Freescale P1022, the DIU video signal and the LBC address/data lines 148 * share the same pins, which means that when the DIU is active (e.g. the 149 * console is on the DVI display), NOR flash cannot be accessed. So we use the 150 * weak accessor feature of the CFI flash code to temporarily switch the pin 151 * mux from DIU to LBC whenever we want to read or write flash. This has a 152 * significant performance penalty, but it's the only way to make it work. 153 * 154 * There are two muxes: one on the chip, and one on the board. The chip mux 155 * controls whether the pins are used for the DIU or the LBC, and it is 156 * set via PMUXCR. The board mux controls whether those signals go to 157 * the video connector or the NOR flash chips, and it is set via the ngPIXIS. 158 */ 159 static int set_mux_to_lbc(void) 160 { 161 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 162 163 /* Switch the muxes only if they're currently set to DIU mode */ 164 if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) != 165 PMUXCR_ELBCDIU_NOR16) { 166 /* 167 * In DIU mode, the PIXIS can only be accessed indirectly 168 * since we can't read/write the LBC directly. 169 */ 170 171 /* Set the board mux to LBC. This will disable the display. */ 172 out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0)); 173 px_brdcfg0 = in_8(lbc_lcs1_ba); 174 out_8(lbc_lcs1_ba, (px_brdcfg0 & ~(PX_BRDCFG0_ELBC_SPI_MASK 175 | PX_BRDCFG0_ELBC_DIU)) | PX_BRDCFG0_ELBC_SPI_ELBC); 176 177 /* Disable indirect PIXIS mode */ 178 out_8(lbc_lcs0_ba, offsetof(ngpixis_t, csr)); 179 clrbits_8(lbc_lcs1_ba, PX_CTL_ALTACC); 180 181 /* Set the chip mux to LBC mode, so that writes go to flash. */ 182 out_be32(&gur->pmuxcr, (pmuxcr & ~PMUXCR_ELBCDIU_MASK) | 183 PMUXCR_ELBCDIU_NOR16); 184 in_be32(&gur->pmuxcr); 185 186 return 1; 187 } 188 189 return 0; 190 } 191 192 /* 193 * set_mux_to_diu - re-enable the DIU muxing 194 * 195 * This function restores the chip and board muxing to point to the DIU. 196 */ 197 static void set_mux_to_diu(void) 198 { 199 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 200 201 /* Enable indirect PIXIS mode */ 202 setbits_8(&pixis->csr, PX_CTL_ALTACC); 203 204 /* Set the board mux to DIU. This will enable the display. */ 205 out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0)); 206 out_8(lbc_lcs1_ba, px_brdcfg0); 207 in_8(lbc_lcs1_ba); 208 209 /* Set the chip mux to DIU mode. */ 210 out_be32(&gur->pmuxcr, pmuxcr); 211 in_be32(&gur->pmuxcr); 212 } 213 214 void flash_write8(u8 value, void *addr) 215 { 216 int sw = set_mux_to_lbc(); 217 218 __raw_writeb(value, addr); 219 if (sw) { 220 /* 221 * To ensure the post-write is completed to eLBC, software must 222 * perform a dummy read from one valid address from eLBC space 223 * before changing the eLBC_DIU from NOR mode to DIU mode. 224 * set_mux_to_diu() includes a sync that will ensure the 225 * __raw_readb() completes before it switches the mux. 226 */ 227 __raw_readb(addr); 228 set_mux_to_diu(); 229 } 230 } 231 232 void flash_write16(u16 value, void *addr) 233 { 234 int sw = set_mux_to_lbc(); 235 236 __raw_writew(value, addr); 237 if (sw) { 238 /* 239 * To ensure the post-write is completed to eLBC, software must 240 * perform a dummy read from one valid address from eLBC space 241 * before changing the eLBC_DIU from NOR mode to DIU mode. 242 * set_mux_to_diu() includes a sync that will ensure the 243 * __raw_readb() completes before it switches the mux. 244 */ 245 __raw_readb(addr); 246 set_mux_to_diu(); 247 } 248 } 249 250 void flash_write32(u32 value, void *addr) 251 { 252 int sw = set_mux_to_lbc(); 253 254 __raw_writel(value, addr); 255 if (sw) { 256 /* 257 * To ensure the post-write is completed to eLBC, software must 258 * perform a dummy read from one valid address from eLBC space 259 * before changing the eLBC_DIU from NOR mode to DIU mode. 260 * set_mux_to_diu() includes a sync that will ensure the 261 * __raw_readb() completes before it switches the mux. 262 */ 263 __raw_readb(addr); 264 set_mux_to_diu(); 265 } 266 } 267 268 void flash_write64(u64 value, void *addr) 269 { 270 int sw = set_mux_to_lbc(); 271 uint32_t *p = addr; 272 273 /* 274 * There is no __raw_writeq(), so do the write manually. We don't trust 275 * the compiler, so we use inline assembly. 276 */ 277 __asm__ __volatile__( 278 "stw%U0%X0 %2,%0;\n" 279 "stw%U1%X1 %3,%1;\n" 280 : "=m" (*p), "=m" (*(p + 1)) 281 : "r" ((uint32_t) (value >> 32)), "r" ((uint32_t) (value))); 282 283 if (sw) { 284 /* 285 * To ensure the post-write is completed to eLBC, software must 286 * perform a dummy read from one valid address from eLBC space 287 * before changing the eLBC_DIU from NOR mode to DIU mode. We 288 * read addr+4 because we just wrote to addr+4, so that's how we 289 * maintain execution order. set_mux_to_diu() includes a sync 290 * that will ensure the __raw_readb() completes before it 291 * switches the mux. 292 */ 293 __raw_readb(addr + 4); 294 set_mux_to_diu(); 295 } 296 } 297 298 u8 flash_read8(void *addr) 299 { 300 u8 ret; 301 302 int sw = set_mux_to_lbc(); 303 304 ret = __raw_readb(addr); 305 if (sw) 306 set_mux_to_diu(); 307 308 return ret; 309 } 310 311 u16 flash_read16(void *addr) 312 { 313 u16 ret; 314 315 int sw = set_mux_to_lbc(); 316 317 ret = __raw_readw(addr); 318 if (sw) 319 set_mux_to_diu(); 320 321 return ret; 322 } 323 324 u32 flash_read32(void *addr) 325 { 326 u32 ret; 327 328 int sw = set_mux_to_lbc(); 329 330 ret = __raw_readl(addr); 331 if (sw) 332 set_mux_to_diu(); 333 334 return ret; 335 } 336 337 u64 flash_read64(void *addr) 338 { 339 u64 ret; 340 341 int sw = set_mux_to_lbc(); 342 343 /* There is no __raw_readq(), so do the read manually */ 344 ret = *(volatile u64 *)addr; 345 if (sw) 346 set_mux_to_diu(); 347 348 return ret; 349 } 350 351 #endif 352