1*83d290c5STom Rini/* SPDX-License-Identifier: GPL-2.0+ */ 2cf94a342SYe Li/* 3cf94a342SYe Li * Copyright (C) 2014 Freescale Semiconductor, Inc. 4cf94a342SYe Li */ 5cf94a342SYe Li 6cf94a342SYe Li#define __ASSEMBLY__ 7cf94a342SYe Li#include <config.h> 8cf94a342SYe Li 9cf94a342SYe Li/* image version */ 10cf94a342SYe Li 11cf94a342SYe LiIMAGE_VERSION 2 12cf94a342SYe Li 13cf94a342SYe Li/* 14cf94a342SYe Li * Boot Device : one of 15cf94a342SYe Li * spi/sd/nand/onenand, qspi/nor 16cf94a342SYe Li */ 17cf94a342SYe Li 18cf94a342SYe LiBOOT_FROM sd 19cf94a342SYe Li 20cf94a342SYe Li/* 21cf94a342SYe Li * Device Configuration Data (DCD) 22cf94a342SYe Li * 23cf94a342SYe Li * Each entry must have the format: 24cf94a342SYe Li * Addr-type Address Value 25cf94a342SYe Li * 26cf94a342SYe Li * where: 27cf94a342SYe Li * Addr-type register length (1,2 or 4 bytes) 28cf94a342SYe Li * Address absolute address of the register 29cf94a342SYe Li * value value to be stored in the register 30cf94a342SYe Li */ 31cf94a342SYe Li 32cf94a342SYe Li/* Enable all clocks */ 33cf94a342SYe LiDATA 4 0x020c4068 0xffffffff 34cf94a342SYe LiDATA 4 0x020c406c 0xffffffff 35cf94a342SYe LiDATA 4 0x020c4070 0xffffffff 36cf94a342SYe LiDATA 4 0x020c4074 0xffffffff 37cf94a342SYe LiDATA 4 0x020c4078 0xffffffff 38cf94a342SYe LiDATA 4 0x020c407c 0xffffffff 39cf94a342SYe LiDATA 4 0x020c4080 0xffffffff 40cf94a342SYe LiDATA 4 0x020c4084 0xffffffff 41cf94a342SYe Li 42cf94a342SYe Li/* IOMUX - DDR IO Type */ 43cf94a342SYe LiDATA 4 0x020e0618 0x000c0000 44cf94a342SYe LiDATA 4 0x020e05fc 0x00000000 45cf94a342SYe Li 46cf94a342SYe Li/* Clock */ 47cf94a342SYe LiDATA 4 0x020e032c 0x00000030 48cf94a342SYe Li 49cf94a342SYe Li/* Address */ 50cf94a342SYe LiDATA 4 0x020e0300 0x00000030 51cf94a342SYe LiDATA 4 0x020e02fc 0x00000030 52cf94a342SYe LiDATA 4 0x020e05f4 0x00000030 53cf94a342SYe Li 54cf94a342SYe Li/* Control */ 55cf94a342SYe LiDATA 4 0x020e0340 0x00000030 56cf94a342SYe Li 57cf94a342SYe LiDATA 4 0x020e0320 0x00000000 58cf94a342SYe LiDATA 4 0x020e0310 0x00000030 59cf94a342SYe LiDATA 4 0x020e0314 0x00000030 60cf94a342SYe LiDATA 4 0x020e0614 0x00000030 61cf94a342SYe Li 62cf94a342SYe Li/* Data Strobe */ 63cf94a342SYe LiDATA 4 0x020e05f8 0x00020000 64cf94a342SYe LiDATA 4 0x020e0330 0x00000030 65cf94a342SYe LiDATA 4 0x020e0334 0x00000030 66cf94a342SYe LiDATA 4 0x020e0338 0x00000030 67cf94a342SYe LiDATA 4 0x020e033c 0x00000030 68cf94a342SYe Li 69cf94a342SYe Li/* Data */ 70cf94a342SYe LiDATA 4 0x020e0608 0x00020000 71cf94a342SYe LiDATA 4 0x020e060c 0x00000030 72cf94a342SYe LiDATA 4 0x020e0610 0x00000030 73cf94a342SYe LiDATA 4 0x020e061c 0x00000030 74cf94a342SYe LiDATA 4 0x020e0620 0x00000030 75cf94a342SYe LiDATA 4 0x020e02ec 0x00000030 76cf94a342SYe LiDATA 4 0x020e02f0 0x00000030 77cf94a342SYe LiDATA 4 0x020e02f4 0x00000030 78cf94a342SYe LiDATA 4 0x020e02f8 0x00000030 79cf94a342SYe Li 80cf94a342SYe Li/* Calibrations - ZQ */ 81cf94a342SYe LiDATA 4 0x021b0800 0xa1390003 82cf94a342SYe Li 83cf94a342SYe Li/* Write leveling */ 84cf94a342SYe LiDATA 4 0x021b080c 0x002C003D 85cf94a342SYe LiDATA 4 0x021b0810 0x00110046 86cf94a342SYe Li 87cf94a342SYe Li/* DQS Read Gate */ 88cf94a342SYe LiDATA 4 0x021b083c 0x4160016C 89cf94a342SYe LiDATA 4 0x021b0840 0x013C016C 90cf94a342SYe Li 91cf94a342SYe Li/* Read/Write Delay */ 92cf94a342SYe LiDATA 4 0x021b0848 0x46424446 93cf94a342SYe LiDATA 4 0x021b0850 0x3A3C3C3A 94cf94a342SYe Li 95cf94a342SYe LiDATA 4 0x021b08c0 0x2492244A 96cf94a342SYe Li 97cf94a342SYe Li/* read data bit delay */ 98cf94a342SYe LiDATA 4 0x021b081c 0x33333333 99cf94a342SYe LiDATA 4 0x021b0820 0x33333333 100cf94a342SYe LiDATA 4 0x021b0824 0x33333333 101cf94a342SYe LiDATA 4 0x021b0828 0x33333333 102cf94a342SYe Li 103cf94a342SYe Li/* Complete calibration by forced measurement */ 104cf94a342SYe LiDATA 4 0x021b08b8 0x00000800 105cf94a342SYe Li 106cf94a342SYe Li/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */ 107cf94a342SYe LiDATA 4 0x021b0004 0x0002002d 108cf94a342SYe LiDATA 4 0x021b0008 0x00333030 109cf94a342SYe LiDATA 4 0x021b000c 0x676b52f3 110cf94a342SYe LiDATA 4 0x021b0010 0xb66d8b63 111cf94a342SYe LiDATA 4 0x021b0014 0x01ff00db 112cf94a342SYe LiDATA 4 0x021b0018 0x00011740 113cf94a342SYe LiDATA 4 0x021b001c 0x00008000 114cf94a342SYe LiDATA 4 0x021b002c 0x000026d2 115cf94a342SYe LiDATA 4 0x021b0030 0x006b1023 116cf94a342SYe LiDATA 4 0x021b0040 0x0000007f 117cf94a342SYe LiDATA 4 0x021b0000 0x85190000 118cf94a342SYe Li 119cf94a342SYe Li/* Initialize MT41K256M16HA-125 - MR2 */ 120cf94a342SYe LiDATA 4 0x021b001c 0x04008032 121cf94a342SYe Li/* MR3 */ 122cf94a342SYe LiDATA 4 0x021b001c 0x00008033 123cf94a342SYe Li/* MR1 */ 124cf94a342SYe LiDATA 4 0x021b001c 0x00068031 125cf94a342SYe Li/* MR0 */ 126cf94a342SYe LiDATA 4 0x021b001c 0x05208030 127cf94a342SYe Li/* DDR device ZQ calibration */ 128cf94a342SYe LiDATA 4 0x021b001c 0x04008040 129cf94a342SYe Li 130cf94a342SYe Li/* Final DDR setup, before operation start */ 131cf94a342SYe LiDATA 4 0x021b0020 0x00000800 132cf94a342SYe LiDATA 4 0x021b0818 0x00022227 133cf94a342SYe LiDATA 4 0x021b0004 0x0002556d 134cf94a342SYe LiDATA 4 0x021b0404 0x00011006 135cf94a342SYe LiDATA 4 0x021b001c 0x00000000 136