xref: /openbmc/u-boot/board/freescale/mx25pdk/mx25pdk.c (revision 86a390d30526ac96ae161fb389c7f151a136208f)
1419adbfbSFabio Estevam /*
2419adbfbSFabio Estevam  * (C) Copyright 2011 Freescale Semiconductor, Inc.
3419adbfbSFabio Estevam  *
4419adbfbSFabio Estevam  * Author: Fabio Estevam <fabio.estevam@freescale.com>
5419adbfbSFabio Estevam  *
61a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
7419adbfbSFabio Estevam  */
8419adbfbSFabio Estevam 
9419adbfbSFabio Estevam #include <common.h>
10419adbfbSFabio Estevam #include <asm/io.h>
11af2a4093SFabio Estevam #include <asm/gpio.h>
12419adbfbSFabio Estevam #include <asm/arch/imx-regs.h>
13d6208a3cSBenoît Thébaudeau #include <asm/arch/iomux-mx25.h>
14af2a4093SFabio Estevam #include <asm/arch/clock.h>
15af2a4093SFabio Estevam #include <mmc.h>
16af2a4093SFabio Estevam #include <fsl_esdhc.h>
17e00c89dfSFabio Estevam #include <i2c.h>
18cabe240bSFabio Estevam #include <power/pmic.h>
19e00c89dfSFabio Estevam #include <fsl_pmic.h>
20e00c89dfSFabio Estevam #include <mc34704.h>
21af2a4093SFabio Estevam 
221b1c5267SBenoît Thébaudeau #define FEC_RESET_B		IMX_GPIO_NR(4, 8)
231b1c5267SBenoît Thébaudeau #define FEC_ENABLE_B		IMX_GPIO_NR(2, 3)
24af2a4093SFabio Estevam #define CARD_DETECT		IMX_GPIO_NR(2, 1)
25419adbfbSFabio Estevam 
26419adbfbSFabio Estevam DECLARE_GLOBAL_DATA_PTR;
27419adbfbSFabio Estevam 
28af2a4093SFabio Estevam #ifdef CONFIG_FSL_ESDHC
29af2a4093SFabio Estevam struct fsl_esdhc_cfg esdhc_cfg[1] = {
30af2a4093SFabio Estevam 	{IMX_MMC_SDHC1_BASE},
31af2a4093SFabio Estevam };
32af2a4093SFabio Estevam #endif
33af2a4093SFabio Estevam 
34d6208a3cSBenoît Thébaudeau /*
35d6208a3cSBenoît Thébaudeau  * FIXME: need to revisit this
36d6208a3cSBenoît Thébaudeau  * The original code enabled PUE and 100-k pull-down without PKE, so the right
37d6208a3cSBenoît Thébaudeau  * value here is likely:
38d6208a3cSBenoît Thébaudeau  *	0 for no pull
39d6208a3cSBenoît Thébaudeau  * or:
40d6208a3cSBenoît Thébaudeau  *	PAD_CTL_PUS_100K_DOWN for 100-k pull-down
41d6208a3cSBenoît Thébaudeau  */
42d6208a3cSBenoît Thébaudeau #define FEC_OUT_PAD_CTRL	0
43d6208a3cSBenoît Thébaudeau 
44d6208a3cSBenoît Thébaudeau #define I2C_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
45d6208a3cSBenoît Thébaudeau 				 PAD_CTL_ODE)
46d6208a3cSBenoît Thébaudeau 
47e00c89dfSFabio Estevam static void mx25pdk_fec_init(void)
48e00c89dfSFabio Estevam {
49d6208a3cSBenoît Thébaudeau 	static const iomux_v3_cfg_t fec_pads[] = {
50d6208a3cSBenoît Thébaudeau 		MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
51d6208a3cSBenoît Thébaudeau 		MX25_PAD_FEC_RX_DV__FEC_RX_DV,
52d6208a3cSBenoît Thébaudeau 		MX25_PAD_FEC_RDATA0__FEC_RDATA0,
53d6208a3cSBenoît Thébaudeau 		NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
54d6208a3cSBenoît Thébaudeau 		NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
55d6208a3cSBenoît Thébaudeau 		NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
56d6208a3cSBenoît Thébaudeau 		MX25_PAD_FEC_MDIO__FEC_MDIO,
57d6208a3cSBenoît Thébaudeau 		MX25_PAD_FEC_RDATA1__FEC_RDATA1,
58d6208a3cSBenoît Thébaudeau 		NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
59e00c89dfSFabio Estevam 
60d6208a3cSBenoît Thébaudeau 		NEW_PAD_CTRL(MX25_PAD_D12__GPIO_4_8, 0), /* FEC_RESET_B */
61d6208a3cSBenoît Thébaudeau 		NEW_PAD_CTRL(MX25_PAD_A17__GPIO_2_3, 0), /* FEC_ENABLE_B */
62d6208a3cSBenoît Thébaudeau 	};
63e00c89dfSFabio Estevam 
64d6208a3cSBenoît Thébaudeau 	static const iomux_v3_cfg_t i2c_pads[] = {
65d6208a3cSBenoît Thébaudeau 		NEW_PAD_CTRL(MX25_PAD_I2C1_CLK__I2C1_CLK, I2C_PAD_CTRL),
66d6208a3cSBenoît Thébaudeau 		NEW_PAD_CTRL(MX25_PAD_I2C1_DAT__I2C1_DAT, I2C_PAD_CTRL),
67d6208a3cSBenoît Thébaudeau 	};
68e00c89dfSFabio Estevam 
69d6208a3cSBenoît Thébaudeau 	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
70e00c89dfSFabio Estevam 
71e00c89dfSFabio Estevam 	/* Assert RESET and ENABLE low */
72e00c89dfSFabio Estevam 	gpio_direction_output(FEC_RESET_B, 0);
73e00c89dfSFabio Estevam 	gpio_direction_output(FEC_ENABLE_B, 0);
74e00c89dfSFabio Estevam 
75e00c89dfSFabio Estevam 	udelay(10);
76e00c89dfSFabio Estevam 
77e00c89dfSFabio Estevam 	/* Deassert RESET and ENABLE */
78e00c89dfSFabio Estevam 	gpio_set_value(FEC_RESET_B, 1);
79e00c89dfSFabio Estevam 	gpio_set_value(FEC_ENABLE_B, 1);
80e00c89dfSFabio Estevam 
81e00c89dfSFabio Estevam 	/* Setup I2C pins so that PMIC can turn on PHY supply */
82d6208a3cSBenoît Thébaudeau 	imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
83e00c89dfSFabio Estevam }
84e00c89dfSFabio Estevam 
85419adbfbSFabio Estevam int dram_init(void)
86419adbfbSFabio Estevam {
87419adbfbSFabio Estevam 	/* dram_init must store complete ramsize in gd->ram_size */
88419adbfbSFabio Estevam 	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
89419adbfbSFabio Estevam 				PHYS_SDRAM_1_SIZE);
90419adbfbSFabio Estevam 	return 0;
91419adbfbSFabio Estevam }
92419adbfbSFabio Estevam 
93d6208a3cSBenoît Thébaudeau /*
94d6208a3cSBenoît Thébaudeau  * Set up input pins with hysteresis and 100-k pull-ups
95d6208a3cSBenoît Thébaudeau  */
96d6208a3cSBenoît Thébaudeau #define UART1_IN_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_100K_UP)
97d6208a3cSBenoît Thébaudeau /*
98d6208a3cSBenoît Thébaudeau  * FIXME: need to revisit this
99d6208a3cSBenoît Thébaudeau  * The original code enabled PUE and 100-k pull-down without PKE, so the right
100d6208a3cSBenoît Thébaudeau  * value here is likely:
101d6208a3cSBenoît Thébaudeau  *	0 for no pull
102d6208a3cSBenoît Thébaudeau  * or:
103d6208a3cSBenoît Thébaudeau  *	PAD_CTL_PUS_100K_DOWN for 100-k pull-down
104d6208a3cSBenoît Thébaudeau  */
105d6208a3cSBenoît Thébaudeau #define UART1_OUT_PAD_CTRL	0
106d6208a3cSBenoît Thébaudeau 
107d6208a3cSBenoît Thébaudeau static void mx25pdk_uart1_init(void)
108d6208a3cSBenoît Thébaudeau {
109d6208a3cSBenoît Thébaudeau 	static const iomux_v3_cfg_t uart1_pads[] = {
110d6208a3cSBenoît Thébaudeau 		NEW_PAD_CTRL(MX25_PAD_UART1_RXD__UART1_RXD, UART1_IN_PAD_CTRL),
111d6208a3cSBenoît Thébaudeau 		NEW_PAD_CTRL(MX25_PAD_UART1_TXD__UART1_TXD, UART1_OUT_PAD_CTRL),
112d6208a3cSBenoît Thébaudeau 		NEW_PAD_CTRL(MX25_PAD_UART1_RTS__UART1_RTS, UART1_OUT_PAD_CTRL),
113d6208a3cSBenoît Thébaudeau 		NEW_PAD_CTRL(MX25_PAD_UART1_CTS__UART1_CTS, UART1_IN_PAD_CTRL),
114d6208a3cSBenoît Thébaudeau 	};
115d6208a3cSBenoît Thébaudeau 
116d6208a3cSBenoît Thébaudeau 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
117d6208a3cSBenoît Thébaudeau }
118d6208a3cSBenoît Thébaudeau 
119419adbfbSFabio Estevam int board_early_init_f(void)
120419adbfbSFabio Estevam {
121d6208a3cSBenoît Thébaudeau 	mx25pdk_uart1_init();
122419adbfbSFabio Estevam 
123419adbfbSFabio Estevam 	return 0;
124419adbfbSFabio Estevam }
125419adbfbSFabio Estevam 
126419adbfbSFabio Estevam int board_init(void)
127419adbfbSFabio Estevam {
128419adbfbSFabio Estevam 	/* address of boot parameters */
129419adbfbSFabio Estevam 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
130419adbfbSFabio Estevam 
131419adbfbSFabio Estevam 	return 0;
132419adbfbSFabio Estevam }
133419adbfbSFabio Estevam 
134e00c89dfSFabio Estevam int board_late_init(void)
135e00c89dfSFabio Estevam {
136e00c89dfSFabio Estevam 	struct pmic *p;
137cabe240bSFabio Estevam 	int ret;
138e00c89dfSFabio Estevam 
139e00c89dfSFabio Estevam 	mx25pdk_fec_init();
140e00c89dfSFabio Estevam 
141570aa2faSFabio Estevam 	ret = pmic_init(I2C_0);
142cabe240bSFabio Estevam 	if (ret)
143cabe240bSFabio Estevam 		return ret;
144cabe240bSFabio Estevam 
145cabe240bSFabio Estevam 	p = pmic_get("FSL_PMIC");
146cabe240bSFabio Estevam 	if (!p)
147cabe240bSFabio Estevam 		return -ENODEV;
148cabe240bSFabio Estevam 
149*86a390d3SFabio Estevam 	/* Turn on Ethernet PHY and LCD supplies */
150*86a390d3SFabio Estevam 	pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE | ONOFFA);
151e00c89dfSFabio Estevam 
152e00c89dfSFabio Estevam 	return 0;
153e00c89dfSFabio Estevam }
154e00c89dfSFabio Estevam 
155af2a4093SFabio Estevam #ifdef CONFIG_FSL_ESDHC
156af2a4093SFabio Estevam int board_mmc_getcd(struct mmc *mmc)
157af2a4093SFabio Estevam {
158d6208a3cSBenoît Thébaudeau 	/* Set up the Card Detect pin. */
159d6208a3cSBenoît Thébaudeau 	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_A15__GPIO_2_1, 0));
160af2a4093SFabio Estevam 
161af2a4093SFabio Estevam 	gpio_direction_input(CARD_DETECT);
162af2a4093SFabio Estevam 	return !gpio_get_value(CARD_DETECT);
163af2a4093SFabio Estevam }
164af2a4093SFabio Estevam 
165af2a4093SFabio Estevam int board_mmc_init(bd_t *bis)
166af2a4093SFabio Estevam {
167d6208a3cSBenoît Thébaudeau 	static const iomux_v3_cfg_t sdhc1_pads[] = {
168d6208a3cSBenoît Thébaudeau 		NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL),
169d6208a3cSBenoît Thébaudeau 		NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL),
170d6208a3cSBenoît Thébaudeau 		NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL),
171d6208a3cSBenoît Thébaudeau 		NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL),
172d6208a3cSBenoît Thébaudeau 		NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL),
173d6208a3cSBenoît Thébaudeau 		NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL),
174d6208a3cSBenoît Thébaudeau 	};
175af2a4093SFabio Estevam 
176d6208a3cSBenoît Thébaudeau 	imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
177af2a4093SFabio Estevam 
178af2a4093SFabio Estevam 	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
179af2a4093SFabio Estevam 	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
180af2a4093SFabio Estevam }
181af2a4093SFabio Estevam #endif
182af2a4093SFabio Estevam 
183419adbfbSFabio Estevam int checkboard(void)
184419adbfbSFabio Estevam {
185419adbfbSFabio Estevam 	puts("Board: MX25PDK\n");
186419adbfbSFabio Estevam 
187419adbfbSFabio Estevam 	return 0;
188419adbfbSFabio Estevam }
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