1 /* 2 * Copyright 2007,2009-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <command.h> 9 #include <pci.h> 10 #include <asm/processor.h> 11 #include <asm/immap_86xx.h> 12 #include <asm/fsl_pci.h> 13 #include <fsl_ddr_sdram.h> 14 #include <asm/fsl_serdes.h> 15 #include <i2c.h> 16 #include <asm/io.h> 17 #include <libfdt.h> 18 #include <fdt_support.h> 19 #include <spd_sdram.h> 20 #include <netdev.h> 21 22 void sdram_init(void); 23 phys_size_t fixed_sdram(void); 24 int mpc8610hpcd_diu_init(void); 25 26 27 /* called before any console output */ 28 int board_early_init_f(void) 29 { 30 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 31 volatile ccsr_gur_t *gur = &immap->im_gur; 32 33 gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */ 34 35 return 0; 36 } 37 38 int misc_init_r(void) 39 { 40 u8 tmp_val, version; 41 u8 *pixis_base = (u8 *)PIXIS_BASE; 42 43 /*Do not use 8259PIC*/ 44 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); 45 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80); 46 47 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/ 48 version = in_8(pixis_base + PIXIS_PVER); 49 if(version >= 0x07) { 50 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); 51 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf); 52 } 53 54 /* Using this for DIU init before the driver in linux takes over 55 * Enable the TFP410 Encoder (I2C address 0x38) 56 */ 57 58 tmp_val = 0xBF; 59 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); 60 /* Verify if enabled */ 61 tmp_val = 0; 62 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); 63 debug("DVI Encoder Read: 0x%02x\n", tmp_val); 64 65 tmp_val = 0x10; 66 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); 67 /* Verify if enabled */ 68 tmp_val = 0; 69 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); 70 debug("DVI Encoder Read: 0x%02x\n", tmp_val); 71 72 return 0; 73 } 74 75 int checkboard(void) 76 { 77 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 78 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; 79 u8 *pixis_base = (u8 *)PIXIS_BASE; 80 81 printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, " 82 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 83 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 84 in_8(pixis_base + PIXIS_PVER)); 85 86 /* 87 * The MPC8610 HPCD workbook says that LBMAP=11 is the "normal" boot 88 * bank and LBMAP=00 is the alternate bank. However, the pixis 89 * altbank code can only set bits, not clear them, so we treat 00 as 90 * the normal bank and 11 as the alternate. 91 */ 92 switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) { 93 case 0: 94 puts("vBank: Standard\n"); 95 break; 96 case 0x40: 97 puts("Promjet\n"); 98 break; 99 case 0x80: 100 puts("NAND\n"); 101 break; 102 case 0xC0: 103 puts("vBank: Alternate\n"); 104 break; 105 } 106 107 mcm->abcr |= 0x00010000; /* 0 */ 108 mcm->hpmr3 = 0x80000008; /* 4c */ 109 mcm->hpmr0 = 0; 110 mcm->hpmr1 = 0; 111 mcm->hpmr2 = 0; 112 mcm->hpmr4 = 0; 113 mcm->hpmr5 = 0; 114 115 return 0; 116 } 117 118 119 phys_size_t initdram(void) 120 { 121 phys_size_t dram_size = 0; 122 123 #if defined(CONFIG_SPD_EEPROM) 124 dram_size = fsl_ddr_sdram(); 125 #else 126 dram_size = fixed_sdram(); 127 #endif 128 129 setup_ddr_bat(dram_size); 130 131 debug(" DDR: "); 132 return dram_size; 133 } 134 135 136 #if !defined(CONFIG_SPD_EEPROM) 137 /* 138 * Fixed sdram init -- doesn't use serial presence detect. 139 */ 140 141 phys_size_t fixed_sdram(void) 142 { 143 #if !defined(CONFIG_SYS_RAMBOOT) 144 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 145 struct ccsr_ddr __iomem *ddr = &immap->im_ddr1; 146 uint d_init; 147 148 ddr->cs0_bnds = 0x0000001f; 149 ddr->cs0_config = 0x80010202; 150 151 ddr->timing_cfg_3 = 0x00000000; 152 ddr->timing_cfg_0 = 0x00260802; 153 ddr->timing_cfg_1 = 0x3935d322; 154 ddr->timing_cfg_2 = 0x14904cc8; 155 ddr->sdram_mode = 0x00480432; 156 ddr->sdram_mode_2 = 0x00000000; 157 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */ 158 ddr->sdram_data_init = 0xDEADBEEF; 159 ddr->sdram_clk_cntl = 0x03800000; 160 ddr->sdram_cfg_2 = 0x04400010; 161 162 #if defined(CONFIG_DDR_ECC) 163 ddr->err_int_en = 0x0000000d; 164 ddr->err_disable = 0x00000000; 165 ddr->err_sbe = 0x00010000; 166 #endif 167 asm("sync;isync"); 168 169 udelay(500); 170 171 ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/ 172 173 174 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 175 d_init = 1; 176 debug("DDR - 1st controller: memory initializing\n"); 177 /* 178 * Poll until memory is initialized. 179 * 512 Meg at 400 might hit this 200 times or so. 180 */ 181 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) 182 udelay(1000); 183 184 debug("DDR: memory initialized\n\n"); 185 asm("sync; isync"); 186 udelay(500); 187 #endif 188 189 return 512 * 1024 * 1024; 190 #endif 191 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 192 } 193 194 #endif 195 196 #if defined(CONFIG_PCI) 197 /* 198 * Initialize PCI Devices, report devices found. 199 */ 200 201 #ifndef CONFIG_PCI_PNP 202 static struct pci_config_table pci_fsl86xxads_config_table[] = { 203 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 204 PCI_IDSEL_NUMBER, PCI_ANY_ID, 205 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 206 PCI_ENET0_MEMADDR, 207 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} }, 208 {} 209 }; 210 #endif 211 212 213 static struct pci_controller pci1_hose; 214 #endif /* CONFIG_PCI */ 215 216 void pci_init_board(void) 217 { 218 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; 219 volatile ccsr_gur_t *gur = &immap->im_gur; 220 struct fsl_pci_info pci_info; 221 u32 devdisr; 222 int first_free_busno; 223 int pci_agent; 224 225 devdisr = in_be32(&gur->devdisr); 226 227 first_free_busno = fsl_pcie_init_board(0); 228 229 #ifdef CONFIG_PCI1 230 if (!(devdisr & MPC86xx_DEVDISR_PCI1)) { 231 SET_STD_PCI_INFO(pci_info, 1); 232 set_next_law(pci_info.mem_phys, 233 law_size_bits(pci_info.mem_size), pci_info.law); 234 set_next_law(pci_info.io_phys, 235 law_size_bits(pci_info.io_size), pci_info.law); 236 237 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); 238 printf("PCI: connected to PCI slots as %s" \ 239 " (base address %lx)\n", 240 pci_agent ? "Agent" : "Host", 241 pci_info.regs); 242 #ifndef CONFIG_PCI_PNP 243 pci1_hose.config_table = pci_mpc86xxcts_config_table; 244 #endif 245 first_free_busno = fsl_pci_init_port(&pci_info, 246 &pci1_hose, first_free_busno); 247 } else { 248 printf("PCI: disabled\n"); 249 } 250 251 puts("\n"); 252 #else 253 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */ 254 #endif 255 256 fsl_pcie_init_board(first_free_busno); 257 } 258 259 #if defined(CONFIG_OF_BOARD_SETUP) 260 int ft_board_setup(void *blob, bd_t *bd) 261 { 262 ft_cpu_setup(blob, bd); 263 264 FT_FSL_PCI_SETUP; 265 266 return 0; 267 } 268 #endif 269 270 /* 271 * get_board_sys_clk 272 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ 273 */ 274 275 unsigned long 276 get_board_sys_clk(ulong dummy) 277 { 278 u8 i; 279 ulong val = 0; 280 u8 *pixis_base = (u8 *)PIXIS_BASE; 281 282 i = in_8(pixis_base + PIXIS_SPD); 283 i &= 0x07; 284 285 switch (i) { 286 case 0: 287 val = 33333000; 288 break; 289 case 1: 290 val = 39999600; 291 break; 292 case 2: 293 val = 49999500; 294 break; 295 case 3: 296 val = 66666000; 297 break; 298 case 4: 299 val = 83332500; 300 break; 301 case 5: 302 val = 99999000; 303 break; 304 case 6: 305 val = 133332000; 306 break; 307 case 7: 308 val = 166665000; 309 break; 310 } 311 312 return val; 313 } 314 315 int board_eth_init(bd_t *bis) 316 { 317 return pci_eth_init(bis); 318 } 319 320 void board_reset(void) 321 { 322 u8 *pixis_base = (u8 *)PIXIS_BASE; 323 324 out_8(pixis_base + PIXIS_RST, 0); 325 326 while (1) 327 ; 328 } 329