1 /* 2 * Copyright 2007-2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <asm/fsl_serdes.h> 34 #include <miiphy.h> 35 #include <libfdt.h> 36 #include <fdt_support.h> 37 #include <tsec.h> 38 #include <netdev.h> 39 40 #include "../common/sgmii_riser.h" 41 42 int checkboard (void) 43 { 44 u8 vboot; 45 u8 *pixis_base = (u8 *)PIXIS_BASE; 46 47 puts ("Board: MPC8572DS "); 48 #ifdef CONFIG_PHYS_64BIT 49 puts ("(36-bit addrmap) "); 50 #endif 51 printf ("Sys ID: 0x%02x, " 52 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 53 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 54 in_8(pixis_base + PIXIS_PVER)); 55 56 vboot = in_8(pixis_base + PIXIS_VBOOT); 57 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) { 58 case PIXIS_VBOOT_LBMAP_NOR0: 59 puts ("vBank: 0\n"); 60 break; 61 case PIXIS_VBOOT_LBMAP_PJET: 62 puts ("Promjet\n"); 63 break; 64 case PIXIS_VBOOT_LBMAP_NAND: 65 puts ("NAND\n"); 66 break; 67 case PIXIS_VBOOT_LBMAP_NOR1: 68 puts ("vBank: 1\n"); 69 break; 70 } 71 72 return 0; 73 } 74 75 76 #if !defined(CONFIG_SPD_EEPROM) 77 /* 78 * Fixed sdram init -- doesn't use serial presence detect. 79 */ 80 81 phys_size_t fixed_sdram (void) 82 { 83 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 84 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 85 uint d_init; 86 87 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 88 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 89 90 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 91 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 92 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 93 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 94 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 95 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 96 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 97 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 98 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 99 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 100 101 #if defined (CONFIG_DDR_ECC) 102 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 103 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 104 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 105 #endif 106 asm("sync;isync"); 107 108 udelay(500); 109 110 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 111 112 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 113 d_init = 1; 114 debug("DDR - 1st controller: memory initializing\n"); 115 /* 116 * Poll until memory is initialized. 117 * 512 Meg at 400 might hit this 200 times or so. 118 */ 119 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 120 udelay(1000); 121 } 122 debug("DDR: memory initialized\n\n"); 123 asm("sync; isync"); 124 udelay(500); 125 #endif 126 127 return 512 * 1024 * 1024; 128 } 129 130 #endif 131 132 #ifdef CONFIG_PCIE1 133 static struct pci_controller pcie1_hose; 134 #endif 135 136 #ifdef CONFIG_PCIE2 137 static struct pci_controller pcie2_hose; 138 #endif 139 140 #ifdef CONFIG_PCIE3 141 static struct pci_controller pcie3_hose; 142 #endif 143 144 #ifdef CONFIG_PCI 145 void pci_init_board(void) 146 { 147 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 148 struct fsl_pci_info pci_info[3]; 149 u32 devdisr, pordevsr, io_sel, temp32; 150 int first_free_busno = 0; 151 int num = 0; 152 153 int pcie_ep, pcie_configured; 154 155 devdisr = in_be32(&gur->devdisr); 156 pordevsr = in_be32(&gur->pordevsr); 157 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 158 159 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 160 161 puts("\n"); 162 #ifdef CONFIG_PCIE3 163 pcie_configured = is_serdes_configured(PCIE3); 164 165 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ 166 SET_STD_PCIE_INFO(pci_info[num], 3); 167 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); 168 printf("PCIE3: connected to ULI as %s (base addr %lx)\n", 169 pcie_ep ? "Endpoint" : "Root Complex", 170 pci_info[num].regs); 171 first_free_busno = fsl_pci_init_port(&pci_info[num++], 172 &pcie3_hose, first_free_busno); 173 /* 174 * Activate ULI1575 legacy chip by performing a fake 175 * memory access. Needed to make ULI RTC work. 176 * Device 1d has the first on-board memory BAR. 177 */ 178 pci_hose_read_config_dword(&pcie3_hose, PCI_BDF(2, 0x1d, 0), 179 PCI_BASE_ADDRESS_1, &temp32); 180 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { 181 void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0), 182 temp32, 4, 0); 183 debug(" uli1572 read to %p\n", p); 184 in_be32(p); 185 } 186 } else { 187 printf("PCIE3: disabled\n"); 188 } 189 puts("\n"); 190 #else 191 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ 192 #endif 193 194 #ifdef CONFIG_PCIE2 195 pcie_configured = is_serdes_configured(PCIE2); 196 197 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ 198 SET_STD_PCIE_INFO(pci_info[num], 2); 199 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); 200 printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n", 201 pcie_ep ? "Endpoint" : "Root Complex", 202 pci_info[num].regs); 203 first_free_busno = fsl_pci_init_port(&pci_info[num++], 204 &pcie2_hose, first_free_busno); 205 } else { 206 printf("PCIE2: disabled\n"); 207 } 208 209 puts("\n"); 210 #else 211 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ 212 #endif 213 214 #ifdef CONFIG_PCIE1 215 pcie_configured = is_serdes_configured(PCIE1); 216 217 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 218 SET_STD_PCIE_INFO(pci_info[num], 1); 219 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); 220 printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n", 221 pcie_ep ? "Endpoint" : "Root Complex", 222 pci_info[num].regs); 223 first_free_busno = fsl_pci_init_port(&pci_info[num++], 224 &pcie1_hose, first_free_busno); 225 } else { 226 printf("PCIE1: disabled\n"); 227 } 228 229 puts("\n"); 230 #else 231 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ 232 #endif 233 } 234 #endif 235 236 int board_early_init_r(void) 237 { 238 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 239 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 240 241 /* 242 * Remap Boot flash + PROMJET region to caching-inhibited 243 * so that flash can be erased properly. 244 */ 245 246 /* Flush d-cache and invalidate i-cache of any FLASH data */ 247 flush_dcache(); 248 invalidate_icache(); 249 250 /* invalidate existing TLB entry for flash + promjet */ 251 disable_tlb(flash_esel); 252 253 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 254 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 255 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 256 257 return 0; 258 } 259 260 #ifdef CONFIG_TSEC_ENET 261 int board_eth_init(bd_t *bis) 262 { 263 struct tsec_info_struct tsec_info[4]; 264 int num = 0; 265 266 #ifdef CONFIG_TSEC1 267 SET_STD_TSEC_INFO(tsec_info[num], 1); 268 if (is_serdes_configured(SGMII_TSEC1)) { 269 puts("eTSEC1 is in sgmii mode.\n"); 270 tsec_info[num].flags |= TSEC_SGMII; 271 } 272 num++; 273 #endif 274 #ifdef CONFIG_TSEC2 275 SET_STD_TSEC_INFO(tsec_info[num], 2); 276 if (is_serdes_configured(SGMII_TSEC2)) { 277 puts("eTSEC2 is in sgmii mode.\n"); 278 tsec_info[num].flags |= TSEC_SGMII; 279 } 280 num++; 281 #endif 282 #ifdef CONFIG_TSEC3 283 SET_STD_TSEC_INFO(tsec_info[num], 3); 284 if (is_serdes_configured(SGMII_TSEC3)) { 285 puts("eTSEC3 is in sgmii mode.\n"); 286 tsec_info[num].flags |= TSEC_SGMII; 287 } 288 num++; 289 #endif 290 #ifdef CONFIG_TSEC4 291 SET_STD_TSEC_INFO(tsec_info[num], 4); 292 if (is_serdes_configured(SGMII_TSEC4)) { 293 puts("eTSEC4 is in sgmii mode.\n"); 294 tsec_info[num].flags |= TSEC_SGMII; 295 } 296 num++; 297 #endif 298 299 if (!num) { 300 printf("No TSECs initialized\n"); 301 302 return 0; 303 } 304 305 #ifdef CONFIG_FSL_SGMII_RISER 306 fsl_sgmii_riser_init(tsec_info, num); 307 #endif 308 309 tsec_eth_init(bis, tsec_info, num); 310 311 return pci_eth_init(bis); 312 } 313 #endif 314 315 #if defined(CONFIG_OF_BOARD_SETUP) 316 void ft_board_setup(void *blob, bd_t *bd) 317 { 318 phys_addr_t base; 319 phys_size_t size; 320 321 ft_cpu_setup(blob, bd); 322 323 base = getenv_bootm_low(); 324 size = getenv_bootm_size(); 325 326 fdt_fixup_memory(blob, (u64)base, (u64)size); 327 328 FT_FSL_PCI_SETUP; 329 330 #ifdef CONFIG_FSL_SGMII_RISER 331 fsl_sgmii_riser_fdt_fixup(blob); 332 #endif 333 } 334 #endif 335 336 #ifdef CONFIG_MP 337 extern void cpu_mp_lmb_reserve(struct lmb *lmb); 338 339 void board_lmb_reserve(struct lmb *lmb) 340 { 341 cpu_mp_lmb_reserve(lmb); 342 } 343 #endif 344