1 /* 2 * Copyright 2007,2009-2010 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <pci.h> 27 #include <asm/processor.h> 28 #include <asm/mmu.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <spd_sdram.h> 33 #include <i2c.h> 34 #include <ioports.h> 35 #include <libfdt.h> 36 #include <fdt_support.h> 37 38 #include "bcsr.h" 39 40 const qe_iop_conf_t qe_iop_conf_tab[] = { 41 /* GETH1 */ 42 {4, 10, 1, 0, 2}, /* TxD0 */ 43 {4, 9, 1, 0, 2}, /* TxD1 */ 44 {4, 8, 1, 0, 2}, /* TxD2 */ 45 {4, 7, 1, 0, 2}, /* TxD3 */ 46 {4, 23, 1, 0, 2}, /* TxD4 */ 47 {4, 22, 1, 0, 2}, /* TxD5 */ 48 {4, 21, 1, 0, 2}, /* TxD6 */ 49 {4, 20, 1, 0, 2}, /* TxD7 */ 50 {4, 15, 2, 0, 2}, /* RxD0 */ 51 {4, 14, 2, 0, 2}, /* RxD1 */ 52 {4, 13, 2, 0, 2}, /* RxD2 */ 53 {4, 12, 2, 0, 2}, /* RxD3 */ 54 {4, 29, 2, 0, 2}, /* RxD4 */ 55 {4, 28, 2, 0, 2}, /* RxD5 */ 56 {4, 27, 2, 0, 2}, /* RxD6 */ 57 {4, 26, 2, 0, 2}, /* RxD7 */ 58 {4, 11, 1, 0, 2}, /* TX_EN */ 59 {4, 24, 1, 0, 2}, /* TX_ER */ 60 {4, 16, 2, 0, 2}, /* RX_DV */ 61 {4, 30, 2, 0, 2}, /* RX_ER */ 62 {4, 17, 2, 0, 2}, /* RX_CLK */ 63 {4, 19, 1, 0, 2}, /* GTX_CLK */ 64 {1, 31, 2, 0, 3}, /* GTX125 */ 65 66 /* GETH2 */ 67 {5, 10, 1, 0, 2}, /* TxD0 */ 68 {5, 9, 1, 0, 2}, /* TxD1 */ 69 {5, 8, 1, 0, 2}, /* TxD2 */ 70 {5, 7, 1, 0, 2}, /* TxD3 */ 71 {5, 23, 1, 0, 2}, /* TxD4 */ 72 {5, 22, 1, 0, 2}, /* TxD5 */ 73 {5, 21, 1, 0, 2}, /* TxD6 */ 74 {5, 20, 1, 0, 2}, /* TxD7 */ 75 {5, 15, 2, 0, 2}, /* RxD0 */ 76 {5, 14, 2, 0, 2}, /* RxD1 */ 77 {5, 13, 2, 0, 2}, /* RxD2 */ 78 {5, 12, 2, 0, 2}, /* RxD3 */ 79 {5, 29, 2, 0, 2}, /* RxD4 */ 80 {5, 28, 2, 0, 2}, /* RxD5 */ 81 {5, 27, 2, 0, 3}, /* RxD6 */ 82 {5, 26, 2, 0, 2}, /* RxD7 */ 83 {5, 11, 1, 0, 2}, /* TX_EN */ 84 {5, 24, 1, 0, 2}, /* TX_ER */ 85 {5, 16, 2, 0, 2}, /* RX_DV */ 86 {5, 30, 2, 0, 2}, /* RX_ER */ 87 {5, 17, 2, 0, 2}, /* RX_CLK */ 88 {5, 19, 1, 0, 2}, /* GTX_CLK */ 89 {1, 31, 2, 0, 3}, /* GTX125 */ 90 {4, 6, 3, 0, 2}, /* MDIO */ 91 {4, 5, 1, 0, 2}, /* MDC */ 92 93 /* UART1 */ 94 {2, 0, 1, 0, 2}, /* UART_SOUT1 */ 95 {2, 1, 1, 0, 2}, /* UART_RTS1 */ 96 {2, 2, 2, 0, 2}, /* UART_CTS1 */ 97 {2, 3, 2, 0, 2}, /* UART_SIN1 */ 98 99 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ 100 }; 101 102 void local_bus_init(void); 103 void sdram_init(void); 104 105 int board_early_init_f (void) 106 { 107 /* 108 * Initialize local bus. 109 */ 110 local_bus_init (); 111 112 enable_8568mds_duart(); 113 enable_8568mds_flash_write(); 114 #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) 115 reset_8568mds_uccs(); 116 #endif 117 #if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS) 118 enable_8568mds_qe_mdio(); 119 #endif 120 121 #ifdef CONFIG_SYS_I2C2_OFFSET 122 /* Enable I2C2_SCL and I2C2_SDA */ 123 volatile struct par_io *port_c; 124 port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140); 125 port_c->cpdir2 |= 0x0f000000; 126 port_c->cppar2 &= ~0x0f000000; 127 port_c->cppar2 |= 0x0a000000; 128 #endif 129 130 return 0; 131 } 132 133 int checkboard (void) 134 { 135 printf ("Board: 8568 MDS\n"); 136 137 return 0; 138 } 139 140 phys_size_t 141 initdram(int board_type) 142 { 143 long dram_size = 0; 144 145 puts("Initializing\n"); 146 147 #if defined(CONFIG_DDR_DLL) 148 { 149 /* 150 * Work around to stabilize DDR DLL MSYNC_IN. 151 * Errata DDR9 seems to have been fixed. 152 * This is now the workaround for Errata DDR11: 153 * Override DLL = 1, Course Adj = 1, Tap Select = 0 154 */ 155 156 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 157 158 gur->ddrdllcr = 0x81000000; 159 asm("sync;isync;msync"); 160 udelay(200); 161 } 162 #endif 163 164 dram_size = fsl_ddr_sdram(); 165 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 166 dram_size *= 0x100000; 167 168 /* 169 * SDRAM Initialization 170 */ 171 sdram_init(); 172 173 puts(" DDR: "); 174 return dram_size; 175 } 176 177 /* 178 * Initialize Local Bus 179 */ 180 void 181 local_bus_init(void) 182 { 183 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 184 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 185 186 uint clkdiv; 187 uint lbc_hz; 188 sys_info_t sysinfo; 189 190 get_sys_info(&sysinfo); 191 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; 192 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 193 194 gur->lbiuiplldcr1 = 0x00078080; 195 if (clkdiv == 16) { 196 gur->lbiuiplldcr0 = 0x7c0f1bf0; 197 } else if (clkdiv == 8) { 198 gur->lbiuiplldcr0 = 0x6c0f1bf0; 199 } else if (clkdiv == 4) { 200 gur->lbiuiplldcr0 = 0x5c0f1bf0; 201 } 202 203 lbc->lcrr |= 0x00030000; 204 205 asm("sync;isync;msync"); 206 } 207 208 /* 209 * Initialize SDRAM memory on the Local Bus. 210 */ 211 void 212 sdram_init(void) 213 { 214 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) 215 216 uint idx; 217 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 218 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 219 uint lsdmr_common; 220 221 puts(" SDRAM: "); 222 223 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 224 225 /* 226 * Setup SDRAM Base and Option Registers 227 */ 228 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); 229 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); 230 asm("msync"); 231 232 lbc->lbcr = CONFIG_SYS_LBC_LBCR; 233 asm("msync"); 234 235 lbc->lsrt = CONFIG_SYS_LBC_LSRT; 236 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; 237 asm("msync"); 238 239 /* 240 * MPC8568 uses "new" 15-16 style addressing. 241 */ 242 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; 243 lsdmr_common |= LSDMR_BSMA1516; 244 245 /* 246 * Issue PRECHARGE ALL command. 247 */ 248 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; 249 asm("sync;msync"); 250 *sdram_addr = 0xff; 251 ppcDcbf((unsigned long) sdram_addr); 252 udelay(100); 253 254 /* 255 * Issue 8 AUTO REFRESH commands. 256 */ 257 for (idx = 0; idx < 8; idx++) { 258 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; 259 asm("sync;msync"); 260 *sdram_addr = 0xff; 261 ppcDcbf((unsigned long) sdram_addr); 262 udelay(100); 263 } 264 265 /* 266 * Issue 8 MODE-set command. 267 */ 268 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; 269 asm("sync;msync"); 270 *sdram_addr = 0xff; 271 ppcDcbf((unsigned long) sdram_addr); 272 udelay(100); 273 274 /* 275 * Issue NORMAL OP command. 276 */ 277 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; 278 asm("sync;msync"); 279 *sdram_addr = 0xff; 280 ppcDcbf((unsigned long) sdram_addr); 281 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 282 283 #endif /* enable SDRAM init */ 284 } 285 286 #if defined(CONFIG_PCI) 287 #ifndef CONFIG_PCI_PNP 288 static struct pci_config_table pci_mpc8568mds_config_table[] = { 289 { 290 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 291 pci_cfgfunc_config_device, 292 {PCI_ENET0_IOADDR, 293 PCI_ENET0_MEMADDR, 294 PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} 295 }, 296 {} 297 }; 298 #endif 299 300 static struct pci_controller pci1_hose = { 301 #ifndef CONFIG_PCI_PNP 302 config_table: pci_mpc8568mds_config_table, 303 #endif 304 }; 305 #endif /* CONFIG_PCI */ 306 307 #ifdef CONFIG_PCIE1 308 static struct pci_controller pcie1_hose; 309 #endif /* CONFIG_PCIE1 */ 310 311 /* 312 * pib_init() -- Initialize the PCA9555 IO expander on the PIB board 313 */ 314 void 315 pib_init(void) 316 { 317 u8 val8, orig_i2c_bus; 318 /* 319 * Assign PIB PMC2/3 to PCI bus 320 */ 321 322 /*switch temporarily to I2C bus #2 */ 323 orig_i2c_bus = i2c_get_bus_num(); 324 i2c_set_bus_num(1); 325 326 val8 = 0x00; 327 i2c_write(0x23, 0x6, 1, &val8, 1); 328 i2c_write(0x23, 0x7, 1, &val8, 1); 329 val8 = 0xff; 330 i2c_write(0x23, 0x2, 1, &val8, 1); 331 i2c_write(0x23, 0x3, 1, &val8, 1); 332 333 val8 = 0x00; 334 i2c_write(0x26, 0x6, 1, &val8, 1); 335 val8 = 0x34; 336 i2c_write(0x26, 0x7, 1, &val8, 1); 337 val8 = 0xf9; 338 i2c_write(0x26, 0x2, 1, &val8, 1); 339 val8 = 0xff; 340 i2c_write(0x26, 0x3, 1, &val8, 1); 341 342 val8 = 0x00; 343 i2c_write(0x27, 0x6, 1, &val8, 1); 344 i2c_write(0x27, 0x7, 1, &val8, 1); 345 val8 = 0xff; 346 i2c_write(0x27, 0x2, 1, &val8, 1); 347 val8 = 0xef; 348 i2c_write(0x27, 0x3, 1, &val8, 1); 349 350 asm("eieio"); 351 } 352 353 #ifdef CONFIG_PCI 354 void pci_init_board(void) 355 { 356 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 357 struct fsl_pci_info pci_info[2]; 358 u32 devdisr, pordevsr, io_sel; 359 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; 360 int first_free_busno = 0; 361 int num = 0; 362 363 int pcie_ep, pcie_configured; 364 365 devdisr = in_be32(&gur->devdisr); 366 pordevsr = in_be32(&gur->pordevsr); 367 porpllsr = in_be32(&gur->porpllsr); 368 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 369 370 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 371 372 #ifdef CONFIG_PCI1 373 pci_speed = 66666000; 374 pci_32 = 1; 375 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 376 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 377 378 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 379 SET_STD_PCI_INFO(pci_info[num], 1); 380 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); 381 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", 382 (pci_32) ? 32 : 64, 383 (pci_speed == 33333000) ? "33" : 384 (pci_speed == 66666000) ? "66" : "unknown", 385 pci_clk_sel ? "sync" : "async", 386 pci_agent ? "agent" : "host", 387 pci_arb ? "arbiter" : "external-arbiter", 388 pci_info[num].regs); 389 390 first_free_busno = fsl_pci_init_port(&pci_info[num++], 391 &pci1_hose, first_free_busno); 392 } else { 393 printf (" PCI: disabled\n"); 394 } 395 396 puts("\n"); 397 #else 398 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 399 #endif 400 401 #ifdef CONFIG_PCIE1 402 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); 403 404 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 405 SET_STD_PCIE_INFO(pci_info[num], 1); 406 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); 407 printf (" PCIE1 connected to Slot as %s (base addr %lx)\n", 408 pcie_ep ? "Endpoint" : "Root Complex", 409 pci_info[num].regs); 410 411 first_free_busno = fsl_pci_init_port(&pci_info[num++], 412 &pcie1_hose, first_free_busno); 413 } else { 414 printf (" PCIE1: disabled\n"); 415 } 416 417 puts("\n"); 418 #else 419 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ 420 #endif 421 } 422 #endif /* CONFIG_PCI */ 423 424 #if defined(CONFIG_OF_BOARD_SETUP) 425 void ft_board_setup(void *blob, bd_t *bd) 426 { 427 ft_cpu_setup(blob, bd); 428 429 FT_FSL_PCI_SETUP; 430 } 431 #endif 432