1 /* 2 * Copyright 2004, 2007, 2009-2010 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <pci.h> 27 #include <asm/processor.h> 28 #include <asm/mmu.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/fsl_serdes.h> 33 #include <spd_sdram.h> 34 #include <miiphy.h> 35 #include <libfdt.h> 36 #include <fdt_support.h> 37 38 #include "../common/cadmus.h" 39 #include "../common/eeprom.h" 40 #include "../common/via.h" 41 42 DECLARE_GLOBAL_DATA_PTR; 43 44 void local_bus_init(void); 45 46 int checkboard (void) 47 { 48 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 49 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 50 51 /* PCI slot in USER bits CSR[6:7] by convention. */ 52 uint pci_slot = get_pci_slot (); 53 54 uint cpu_board_rev = get_cpu_board_revision (); 55 56 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", 57 get_board_version (), pci_slot); 58 59 printf ("CPU Board Revision %d.%d (0x%04x)\n", 60 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), 61 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); 62 /* 63 * Initialize local bus. 64 */ 65 local_bus_init (); 66 67 /* 68 * Hack TSEC 3 and 4 IO voltages. 69 */ 70 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ 71 72 ecm->eedr = 0xffffffff; /* clear ecm errors */ 73 ecm->eeer = 0xffffffff; /* enable ecm errors */ 74 return 0; 75 } 76 77 /* 78 * Initialize Local Bus 79 */ 80 void 81 local_bus_init(void) 82 { 83 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 84 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 85 86 uint clkdiv; 87 uint lbc_hz; 88 sys_info_t sysinfo; 89 90 get_sys_info(&sysinfo); 91 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; 92 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 93 94 gur->lbiuiplldcr1 = 0x00078080; 95 if (clkdiv == 16) { 96 gur->lbiuiplldcr0 = 0x7c0f1bf0; 97 } else if (clkdiv == 8) { 98 gur->lbiuiplldcr0 = 0x6c0f1bf0; 99 } else if (clkdiv == 4) { 100 gur->lbiuiplldcr0 = 0x5c0f1bf0; 101 } 102 103 lbc->lcrr |= 0x00030000; 104 105 asm("sync;isync;msync"); 106 107 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ 108 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ 109 } 110 111 /* 112 * Initialize SDRAM memory on the Local Bus. 113 */ 114 void lbc_sdram_init(void) 115 { 116 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) 117 118 uint idx; 119 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 120 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 121 uint cpu_board_rev; 122 uint lsdmr_common; 123 124 puts(" SDRAM: "); 125 126 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); 127 128 /* 129 * Setup SDRAM Base and Option Registers 130 */ 131 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); 132 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); 133 lbc->lbcr = CONFIG_SYS_LBC_LBCR; 134 asm("msync"); 135 136 lbc->lsrt = CONFIG_SYS_LBC_LSRT; 137 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; 138 asm("msync"); 139 140 /* 141 * MPC8548 uses "new" 15-16 style addressing. 142 */ 143 cpu_board_rev = get_cpu_board_revision(); 144 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; 145 lsdmr_common |= LSDMR_BSMA1516; 146 147 /* 148 * Issue PRECHARGE ALL command. 149 */ 150 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; 151 asm("sync;msync"); 152 *sdram_addr = 0xff; 153 ppcDcbf((unsigned long) sdram_addr); 154 udelay(100); 155 156 /* 157 * Issue 8 AUTO REFRESH commands. 158 */ 159 for (idx = 0; idx < 8; idx++) { 160 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; 161 asm("sync;msync"); 162 *sdram_addr = 0xff; 163 ppcDcbf((unsigned long) sdram_addr); 164 udelay(100); 165 } 166 167 /* 168 * Issue 8 MODE-set command. 169 */ 170 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; 171 asm("sync;msync"); 172 *sdram_addr = 0xff; 173 ppcDcbf((unsigned long) sdram_addr); 174 udelay(100); 175 176 /* 177 * Issue NORMAL OP command. 178 */ 179 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; 180 asm("sync;msync"); 181 *sdram_addr = 0xff; 182 ppcDcbf((unsigned long) sdram_addr); 183 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 184 185 #endif /* enable SDRAM init */ 186 } 187 188 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1) 189 /* For some reason the Tundra PCI bridge shows up on itself as a 190 * different device. Work around that by refusing to configure it. 191 */ 192 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } 193 194 static struct pci_config_table pci_mpc85xxcds_config_table[] = { 195 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, 196 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, 197 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, 198 mpc85xx_config_via_usbide, {0,0,0}}, 199 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, 200 mpc85xx_config_via_usb, {0,0,0}}, 201 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, 202 mpc85xx_config_via_usb2, {0,0,0}}, 203 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, 204 mpc85xx_config_via_power, {0,0,0}}, 205 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, 206 mpc85xx_config_via_ac97, {0,0,0}}, 207 {}, 208 }; 209 210 static struct pci_controller pci1_hose = { 211 config_table: pci_mpc85xxcds_config_table}; 212 #endif /* CONFIG_PCI */ 213 214 #ifdef CONFIG_PCI2 215 static struct pci_controller pci2_hose; 216 #endif /* CONFIG_PCI2 */ 217 218 #ifdef CONFIG_PCIE1 219 static struct pci_controller pcie1_hose; 220 #endif /* CONFIG_PCIE1 */ 221 222 void pci_init_board(void) 223 { 224 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 225 struct fsl_pci_info pci_info[4]; 226 u32 devdisr, pordevsr, io_sel; 227 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; 228 int first_free_busno = 0; 229 int num = 0; 230 231 int pcie_ep, pcie_configured; 232 233 devdisr = in_be32(&gur->devdisr); 234 pordevsr = in_be32(&gur->pordevsr); 235 porpllsr = in_be32(&gur->porpllsr); 236 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 237 238 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 239 240 #ifdef CONFIG_PCI1 241 pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ 242 pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ 243 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 244 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 245 246 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 247 SET_STD_PCI_INFO(pci_info[num], 1); 248 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); 249 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", 250 (pci_32) ? 32 : 64, 251 (pci_speed == 33333000) ? "33" : 252 (pci_speed == 66666000) ? "66" : "unknown", 253 pci_clk_sel ? "sync" : "async", 254 pci_agent ? "agent" : "host", 255 pci_arb ? "arbiter" : "external-arbiter", 256 pci_info[num].regs); 257 258 first_free_busno = fsl_pci_init_port(&pci_info[num++], 259 &pci1_hose, first_free_busno); 260 261 #ifdef CONFIG_PCIX_CHECK 262 if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) { 263 /* PCI-X init */ 264 if (CONFIG_SYS_CLK_FREQ < 66000000) 265 printf("PCI-X will only work at 66 MHz\n"); 266 267 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 268 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 269 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); 270 } 271 #endif 272 } else { 273 printf("PCI: disabled\n"); 274 } 275 276 puts("\n"); 277 #else 278 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 279 #endif 280 281 #ifdef CONFIG_PCI2 282 { 283 uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */ 284 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ 285 if (pci_dual) { 286 printf("PCI2: 32 bit, 66 MHz, %s\n", 287 pci2_clk_sel ? "sync" : "async"); 288 } else { 289 printf("PCI2: disabled\n"); 290 } 291 } 292 #else 293 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */ 294 #endif /* CONFIG_PCI2 */ 295 296 #ifdef CONFIG_PCIE1 297 pcie_configured = is_serdes_configured(PCIE1); 298 299 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 300 SET_STD_PCIE_INFO(pci_info[num], 1); 301 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); 302 printf("PCIE1: connected to Slot as %s (base addr %lx)\n", 303 pcie_ep ? "Endpoint" : "Root Complex", 304 pci_info[num].regs); 305 306 first_free_busno = fsl_pci_init_port(&pci_info[num++], 307 &pcie1_hose, first_free_busno); 308 } else { 309 printf("PCIE1: disabled\n"); 310 } 311 312 puts("\n"); 313 #else 314 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ 315 #endif 316 } 317 318 int last_stage_init(void) 319 { 320 unsigned short temp; 321 322 /* Change the resistors for the PHY */ 323 /* This is needed to get the RGMII working for the 1.3+ 324 * CDS cards */ 325 if (get_board_version() == 0x13) { 326 miiphy_write(CONFIG_TSEC1_NAME, 327 TSEC1_PHY_ADDR, 29, 18); 328 329 miiphy_read(CONFIG_TSEC1_NAME, 330 TSEC1_PHY_ADDR, 30, &temp); 331 332 temp = (temp & 0xf03f); 333 temp |= 2 << 9; /* 36 ohm */ 334 temp |= 2 << 6; /* 39 ohm */ 335 336 miiphy_write(CONFIG_TSEC1_NAME, 337 TSEC1_PHY_ADDR, 30, temp); 338 339 miiphy_write(CONFIG_TSEC1_NAME, 340 TSEC1_PHY_ADDR, 29, 3); 341 342 miiphy_write(CONFIG_TSEC1_NAME, 343 TSEC1_PHY_ADDR, 30, 0x8000); 344 } 345 346 return 0; 347 } 348 349 350 #if defined(CONFIG_OF_BOARD_SETUP) 351 void ft_pci_setup(void *blob, bd_t *bd) 352 { 353 FT_FSL_PCI_SETUP; 354 } 355 #endif 356