1 /* 2 * Copyright 2004, 2007, 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <pci.h> 27 #include <asm/processor.h> 28 #include <asm/mmu.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/fsl_serdes.h> 33 #include <miiphy.h> 34 #include <libfdt.h> 35 #include <fdt_support.h> 36 37 #include "../common/cadmus.h" 38 #include "../common/eeprom.h" 39 #include "../common/via.h" 40 41 void local_bus_init(void); 42 43 int checkboard (void) 44 { 45 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 46 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 47 48 /* PCI slot in USER bits CSR[6:7] by convention. */ 49 uint pci_slot = get_pci_slot (); 50 51 uint cpu_board_rev = get_cpu_board_revision (); 52 53 puts("Board: MPC8548CDS"); 54 printf(" Carrier Rev: 0x%02x, PCI Slot %d\n", 55 get_board_version(), pci_slot); 56 printf(" Daughtercard Rev: %d.%d (0x%04x)\n", 57 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), 58 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); 59 /* 60 * Initialize local bus. 61 */ 62 local_bus_init (); 63 64 /* 65 * Hack TSEC 3 and 4 IO voltages. 66 */ 67 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ 68 69 ecm->eedr = 0xffffffff; /* clear ecm errors */ 70 ecm->eeer = 0xffffffff; /* enable ecm errors */ 71 return 0; 72 } 73 74 /* 75 * Initialize Local Bus 76 */ 77 void 78 local_bus_init(void) 79 { 80 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 81 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 82 83 uint clkdiv; 84 uint lbc_hz; 85 sys_info_t sysinfo; 86 87 get_sys_info(&sysinfo); 88 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; 89 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; 90 91 gur->lbiuiplldcr1 = 0x00078080; 92 if (clkdiv == 16) { 93 gur->lbiuiplldcr0 = 0x7c0f1bf0; 94 } else if (clkdiv == 8) { 95 gur->lbiuiplldcr0 = 0x6c0f1bf0; 96 } else if (clkdiv == 4) { 97 gur->lbiuiplldcr0 = 0x5c0f1bf0; 98 } 99 100 lbc->lcrr |= 0x00030000; 101 102 asm("sync;isync;msync"); 103 104 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ 105 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ 106 } 107 108 /* 109 * Initialize SDRAM memory on the Local Bus. 110 */ 111 void lbc_sdram_init(void) 112 { 113 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) 114 115 uint idx; 116 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; 117 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; 118 uint cpu_board_rev; 119 uint lsdmr_common; 120 121 puts("LBC SDRAM: "); 122 print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, 123 "\n"); 124 125 /* 126 * Setup SDRAM Base and Option Registers 127 */ 128 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); 129 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); 130 lbc->lbcr = CONFIG_SYS_LBC_LBCR; 131 asm("msync"); 132 133 lbc->lsrt = CONFIG_SYS_LBC_LSRT; 134 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; 135 asm("msync"); 136 137 /* 138 * MPC8548 uses "new" 15-16 style addressing. 139 */ 140 cpu_board_rev = get_cpu_board_revision(); 141 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; 142 lsdmr_common |= LSDMR_BSMA1516; 143 144 /* 145 * Issue PRECHARGE ALL command. 146 */ 147 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; 148 asm("sync;msync"); 149 *sdram_addr = 0xff; 150 ppcDcbf((unsigned long) sdram_addr); 151 udelay(100); 152 153 /* 154 * Issue 8 AUTO REFRESH commands. 155 */ 156 for (idx = 0; idx < 8; idx++) { 157 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; 158 asm("sync;msync"); 159 *sdram_addr = 0xff; 160 ppcDcbf((unsigned long) sdram_addr); 161 udelay(100); 162 } 163 164 /* 165 * Issue 8 MODE-set command. 166 */ 167 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; 168 asm("sync;msync"); 169 *sdram_addr = 0xff; 170 ppcDcbf((unsigned long) sdram_addr); 171 udelay(100); 172 173 /* 174 * Issue NORMAL OP command. 175 */ 176 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; 177 asm("sync;msync"); 178 *sdram_addr = 0xff; 179 ppcDcbf((unsigned long) sdram_addr); 180 udelay(200); /* Overkill. Must wait > 200 bus cycles */ 181 182 #endif /* enable SDRAM init */ 183 } 184 185 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1) 186 /* For some reason the Tundra PCI bridge shows up on itself as a 187 * different device. Work around that by refusing to configure it. 188 */ 189 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } 190 191 static struct pci_config_table pci_mpc85xxcds_config_table[] = { 192 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, 193 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, 194 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, 195 mpc85xx_config_via_usbide, {0,0,0}}, 196 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, 197 mpc85xx_config_via_usb, {0,0,0}}, 198 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, 199 mpc85xx_config_via_usb2, {0,0,0}}, 200 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, 201 mpc85xx_config_via_power, {0,0,0}}, 202 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, 203 mpc85xx_config_via_ac97, {0,0,0}}, 204 {}, 205 }; 206 207 static struct pci_controller pci1_hose; 208 #endif /* CONFIG_PCI */ 209 210 void pci_init_board(void) 211 { 212 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 213 struct fsl_pci_info pci_info; 214 u32 devdisr, pordevsr, io_sel; 215 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; 216 int first_free_busno = 0; 217 char buf[32]; 218 219 devdisr = in_be32(&gur->devdisr); 220 pordevsr = in_be32(&gur->pordevsr); 221 porpllsr = in_be32(&gur->porpllsr); 222 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 223 224 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 225 226 #ifdef CONFIG_PCI1 227 pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ 228 pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ 229 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 230 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 231 232 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 233 SET_STD_PCI_INFO(pci_info, 1); 234 set_next_law(pci_info.mem_phys, 235 law_size_bits(pci_info.mem_size), pci_info.law); 236 set_next_law(pci_info.io_phys, 237 law_size_bits(pci_info.io_size), pci_info.law); 238 239 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); 240 printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", 241 (pci_32) ? 32 : 64, 242 strmhz(buf, pci_speed), 243 pci_clk_sel ? "sync" : "async", 244 pci_agent ? "agent" : "host", 245 pci_arb ? "arbiter" : "external-arbiter", 246 pci_info.regs); 247 248 pci1_hose.config_table = pci_mpc85xxcds_config_table; 249 first_free_busno = fsl_pci_init_port(&pci_info, 250 &pci1_hose, first_free_busno); 251 252 #ifdef CONFIG_PCIX_CHECK 253 if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) { 254 /* PCI-X init */ 255 if (CONFIG_SYS_CLK_FREQ < 66000000) 256 printf("PCI-X will only work at 66 MHz\n"); 257 258 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 259 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 260 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); 261 } 262 #endif 263 } else { 264 printf("PCI1: disabled\n"); 265 } 266 267 puts("\n"); 268 #else 269 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 270 #endif 271 272 #ifdef CONFIG_PCI2 273 { 274 uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */ 275 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ 276 if (pci_dual) { 277 printf("PCI2: 32 bit, 66 MHz, %s\n", 278 pci2_clk_sel ? "sync" : "async"); 279 } else { 280 printf("PCI2: disabled\n"); 281 } 282 } 283 #else 284 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */ 285 #endif /* CONFIG_PCI2 */ 286 287 fsl_pcie_init_board(first_free_busno); 288 } 289 290 int last_stage_init(void) 291 { 292 unsigned short temp; 293 294 /* Change the resistors for the PHY */ 295 /* This is needed to get the RGMII working for the 1.3+ 296 * CDS cards */ 297 if (get_board_version() == 0x13) { 298 miiphy_write(CONFIG_TSEC1_NAME, 299 TSEC1_PHY_ADDR, 29, 18); 300 301 miiphy_read(CONFIG_TSEC1_NAME, 302 TSEC1_PHY_ADDR, 30, &temp); 303 304 temp = (temp & 0xf03f); 305 temp |= 2 << 9; /* 36 ohm */ 306 temp |= 2 << 6; /* 39 ohm */ 307 308 miiphy_write(CONFIG_TSEC1_NAME, 309 TSEC1_PHY_ADDR, 30, temp); 310 311 miiphy_write(CONFIG_TSEC1_NAME, 312 TSEC1_PHY_ADDR, 29, 3); 313 314 miiphy_write(CONFIG_TSEC1_NAME, 315 TSEC1_PHY_ADDR, 30, 0x8000); 316 } 317 318 return 0; 319 } 320 321 322 #if defined(CONFIG_OF_BOARD_SETUP) 323 void ft_pci_setup(void *blob, bd_t *bd) 324 { 325 FT_FSL_PCI_SETUP; 326 } 327 #endif 328