1 /* 2 * Copyright 2008 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 #include <common.h> 10 #include <i2c.h> 11 12 #include <asm/fsl_ddr_sdram.h> 13 #include <asm/fsl_ddr_dimm_params.h> 14 15 static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) 16 { 17 i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); 18 } 19 20 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, 21 unsigned int ctrl_num) 22 { 23 unsigned int i; 24 25 if (ctrl_num) { 26 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); 27 return; 28 } 29 30 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { 31 get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); 32 } 33 } 34 35 void fsl_ddr_board_options(memctl_options_t *popts, 36 dimm_params_t *pdimm, 37 unsigned int ctrl_num) 38 { 39 /* 40 * Factors to consider for clock adjust: 41 * - number of chips on bus 42 * - position of slot 43 * - DDR1 vs. DDR2? 44 * - ??? 45 * 46 * This needs to be determined on a board-by-board basis. 47 * 0110 3/4 cycle late 48 * 0111 7/8 cycle late 49 */ 50 popts->clk_adjust = 7; 51 52 /* 53 * Factors to consider for CPO: 54 * - frequency 55 * - ddr1 vs. ddr2 56 */ 57 popts->cpo_override = 10; 58 59 /* 60 * Factors to consider for write data delay: 61 * - number of DIMMs 62 * 63 * 1 = 1/4 clock delay 64 * 2 = 1/2 clock delay 65 * 3 = 3/4 clock delay 66 * 4 = 1 clock delay 67 * 5 = 5/4 clock delay 68 * 6 = 3/2 clock delay 69 */ 70 popts->write_data_delay = 3; 71 72 /* 73 * Factors to consider for half-strength driver enable: 74 * - number of DIMMs installed 75 */ 76 popts->half_strength_driver_enable = 0; 77 78 /* 79 * For wake up arp feature, we need enable auto self refresh 80 */ 81 popts->auto_self_refresh_en = 1; 82 popts->sr_it = 0x6; 83 } 84