1*19580e66SDave Liu /* 2*19580e66SDave Liu * Copyright (C) 2007 Freescale Semiconductor, Inc. 3*19580e66SDave Liu * Dave Liu <daveliu@freescale.com> 4*19580e66SDave Liu * 5*19580e66SDave Liu * CREDITS: Kim Phillips contribute to LIBFDT code 6*19580e66SDave Liu * 7*19580e66SDave Liu * This program is free software; you can redistribute it and/or 8*19580e66SDave Liu * modify it under the terms of the GNU General Public License as 9*19580e66SDave Liu * published by the Free Software Foundation; either version 2 of 10*19580e66SDave Liu * the License, or (at your option) any later version. 11*19580e66SDave Liu */ 12*19580e66SDave Liu 13*19580e66SDave Liu #include <common.h> 14*19580e66SDave Liu #include <i2c.h> 15*19580e66SDave Liu #include <spd.h> 16*19580e66SDave Liu #if defined(CONFIG_SPD_EEPROM) 17*19580e66SDave Liu #include <spd_sdram.h> 18*19580e66SDave Liu #endif 19*19580e66SDave Liu #if defined(CONFIG_OF_FLAT_TREE) 20*19580e66SDave Liu #include <ft_build.h> 21*19580e66SDave Liu #elif defined(CONFIG_OF_LIBFDT) 22*19580e66SDave Liu #include <libfdt.h> 23*19580e66SDave Liu #endif 24*19580e66SDave Liu #if defined(CONFIG_PQ_MDS_PIB) 25*19580e66SDave Liu #include "../common/pq-mds-pib.h" 26*19580e66SDave Liu #endif 27*19580e66SDave Liu 28*19580e66SDave Liu int board_early_init_f(void) 29*19580e66SDave Liu { 30*19580e66SDave Liu u8 *bcsr = (u8 *)CFG_BCSR; 31*19580e66SDave Liu 32*19580e66SDave Liu /* Enable flash write */ 33*19580e66SDave Liu bcsr[0x9] &= ~0x04; 34*19580e66SDave Liu /* Clear all of the interrupt of BCSR */ 35*19580e66SDave Liu bcsr[0xe] = 0xff; 36*19580e66SDave Liu 37*19580e66SDave Liu return 0; 38*19580e66SDave Liu } 39*19580e66SDave Liu 40*19580e66SDave Liu int board_early_init_r(void) 41*19580e66SDave Liu { 42*19580e66SDave Liu #ifdef CONFIG_PQ_MDS_PIB 43*19580e66SDave Liu pib_init(); 44*19580e66SDave Liu #endif 45*19580e66SDave Liu return 0; 46*19580e66SDave Liu } 47*19580e66SDave Liu 48*19580e66SDave Liu #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) 49*19580e66SDave Liu extern void ddr_enable_ecc(unsigned int dram_size); 50*19580e66SDave Liu #endif 51*19580e66SDave Liu int fixed_sdram(void); 52*19580e66SDave Liu 53*19580e66SDave Liu long int initdram(int board_type) 54*19580e66SDave Liu { 55*19580e66SDave Liu volatile immap_t *im = (immap_t *) CFG_IMMR; 56*19580e66SDave Liu u32 msize = 0; 57*19580e66SDave Liu 58*19580e66SDave Liu if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) 59*19580e66SDave Liu return -1; 60*19580e66SDave Liu 61*19580e66SDave Liu #if defined(CONFIG_SPD_EEPROM) 62*19580e66SDave Liu msize = spd_sdram(); 63*19580e66SDave Liu #else 64*19580e66SDave Liu msize = fixed_sdram(); 65*19580e66SDave Liu #endif 66*19580e66SDave Liu 67*19580e66SDave Liu #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) 68*19580e66SDave Liu /* Initialize DDR ECC byte */ 69*19580e66SDave Liu ddr_enable_ecc(msize * 1024 * 1024); 70*19580e66SDave Liu #endif 71*19580e66SDave Liu 72*19580e66SDave Liu /* return total bus DDR size(bytes) */ 73*19580e66SDave Liu return (msize * 1024 * 1024); 74*19580e66SDave Liu } 75*19580e66SDave Liu 76*19580e66SDave Liu #if !defined(CONFIG_SPD_EEPROM) 77*19580e66SDave Liu /************************************************************************* 78*19580e66SDave Liu * fixed sdram init -- doesn't use serial presence detect. 79*19580e66SDave Liu ************************************************************************/ 80*19580e66SDave Liu int fixed_sdram(void) 81*19580e66SDave Liu { 82*19580e66SDave Liu volatile immap_t *im = (immap_t *) CFG_IMMR; 83*19580e66SDave Liu u32 msize = CFG_DDR_SIZE * 1024 * 1024; 84*19580e66SDave Liu u32 msize_log2 = __ilog2(msize); 85*19580e66SDave Liu 86*19580e66SDave Liu im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12; 87*19580e66SDave Liu im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); 88*19580e66SDave Liu 89*19580e66SDave Liu #if (CFG_DDR_SIZE != 512) 90*19580e66SDave Liu #warning Currenly any ddr size other than 512 is not supported 91*19580e66SDave Liu #endif 92*19580e66SDave Liu im->sysconf.ddrcdr = CFG_DDRCDR_VALUE; 93*19580e66SDave Liu udelay(50000); 94*19580e66SDave Liu 95*19580e66SDave Liu im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; 96*19580e66SDave Liu udelay(1000); 97*19580e66SDave Liu 98*19580e66SDave Liu im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; 99*19580e66SDave Liu im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; 100*19580e66SDave Liu udelay(1000); 101*19580e66SDave Liu 102*19580e66SDave Liu im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; 103*19580e66SDave Liu im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; 104*19580e66SDave Liu im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; 105*19580e66SDave Liu im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; 106*19580e66SDave Liu im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; 107*19580e66SDave Liu im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; 108*19580e66SDave Liu im->ddr.sdram_mode = CFG_DDR_MODE; 109*19580e66SDave Liu im->ddr.sdram_mode2 = CFG_DDR_MODE2; 110*19580e66SDave Liu im->ddr.sdram_interval = CFG_DDR_INTERVAL; 111*19580e66SDave Liu __asm__ __volatile__("sync"); 112*19580e66SDave Liu udelay(1000); 113*19580e66SDave Liu 114*19580e66SDave Liu im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 115*19580e66SDave Liu udelay(2000); 116*19580e66SDave Liu return CFG_DDR_SIZE; 117*19580e66SDave Liu } 118*19580e66SDave Liu #endif /*!CFG_SPD_EEPROM */ 119*19580e66SDave Liu 120*19580e66SDave Liu int checkboard(void) 121*19580e66SDave Liu { 122*19580e66SDave Liu puts("Board: Freescale MPC837xEMDS\n"); 123*19580e66SDave Liu return 0; 124*19580e66SDave Liu } 125*19580e66SDave Liu 126*19580e66SDave Liu #if defined(CONFIG_OF_BOARD_SETUP) 127*19580e66SDave Liu void ft_board_setup(void *blob, bd_t *bd) 128*19580e66SDave Liu { 129*19580e66SDave Liu #if defined(CONFIG_OF_FLAT_TREE) 130*19580e66SDave Liu u32 *p; 131*19580e66SDave Liu int len; 132*19580e66SDave Liu 133*19580e66SDave Liu p = ft_get_prop(blob, "/memory/reg", &len); 134*19580e66SDave Liu if (p != NULL) { 135*19580e66SDave Liu *p++ = cpu_to_be32(bd->bi_memstart); 136*19580e66SDave Liu *p = cpu_to_be32(bd->bi_memsize); 137*19580e66SDave Liu } 138*19580e66SDave Liu #endif 139*19580e66SDave Liu ft_cpu_setup(blob, bd); 140*19580e66SDave Liu #ifdef CONFIG_PCI 141*19580e66SDave Liu ft_pci_setup(blob, bd); 142*19580e66SDave Liu #endif 143*19580e66SDave Liu } 144*19580e66SDave Liu #endif /* CONFIG_OF_BOARD_SETUP */ 145