1 /* 2 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 9 #include <asm/mmu.h> 10 #include <asm/io.h> 11 #include <mpc83xx.h> 12 #include <pci.h> 13 #include <i2c.h> 14 #include <asm/fsl_i2c.h> 15 16 static struct pci_region pci1_regions[] = { 17 { 18 bus_start: CONFIG_SYS_PCI1_MEM_BASE, 19 phys_start: CONFIG_SYS_PCI1_MEM_PHYS, 20 size: CONFIG_SYS_PCI1_MEM_SIZE, 21 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH 22 }, 23 { 24 bus_start: CONFIG_SYS_PCI1_IO_BASE, 25 phys_start: CONFIG_SYS_PCI1_IO_PHYS, 26 size: CONFIG_SYS_PCI1_IO_SIZE, 27 flags: PCI_REGION_IO 28 }, 29 { 30 bus_start: CONFIG_SYS_PCI1_MMIO_BASE, 31 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, 32 size: CONFIG_SYS_PCI1_MMIO_SIZE, 33 flags: PCI_REGION_MEM 34 }, 35 }; 36 37 #ifdef CONFIG_MPC83XX_PCI2 38 static struct pci_region pci2_regions[] = { 39 { 40 bus_start: CONFIG_SYS_PCI2_MEM_BASE, 41 phys_start: CONFIG_SYS_PCI2_MEM_PHYS, 42 size: CONFIG_SYS_PCI2_MEM_SIZE, 43 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH 44 }, 45 { 46 bus_start: CONFIG_SYS_PCI2_IO_BASE, 47 phys_start: CONFIG_SYS_PCI2_IO_PHYS, 48 size: CONFIG_SYS_PCI2_IO_SIZE, 49 flags: PCI_REGION_IO 50 }, 51 { 52 bus_start: CONFIG_SYS_PCI2_MMIO_BASE, 53 phys_start: CONFIG_SYS_PCI2_MMIO_PHYS, 54 size: CONFIG_SYS_PCI2_MMIO_SIZE, 55 flags: PCI_REGION_MEM 56 }, 57 }; 58 #endif 59 60 void pci_init_board(void) 61 { 62 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; 63 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; 64 volatile law83xx_t *pci_law = immr->sysconf.pcilaw; 65 #ifndef CONFIG_MPC83XX_PCI2 66 struct pci_region *reg[] = { pci1_regions }; 67 #else 68 struct pci_region *reg[] = { pci1_regions, pci2_regions }; 69 #endif 70 u8 reg8; 71 72 #if defined(CONFIG_SYS_I2C) 73 i2c_set_bus_num(1); 74 /* Read the PCI_M66EN jumper setting */ 75 if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) || 76 (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) { 77 if (reg8 & I2C_8574_PCI66) 78 clk->occr = 0xff000000; /* 66 MHz PCI */ 79 else 80 clk->occr = 0xff600001; /* 33 MHz PCI */ 81 } else { 82 clk->occr = 0xff600001; /* 33 MHz PCI */ 83 } 84 #else 85 clk->occr = 0xff000000; /* 66 MHz PCI */ 86 #endif 87 udelay(2000); 88 89 /* Configure PCI Local Access Windows */ 90 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; 91 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; 92 93 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; 94 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M; 95 96 udelay(2000); 97 98 #ifndef CONFIG_MPC83XX_PCI2 99 mpc83xx_pci_init(1, reg); 100 #else 101 mpc83xx_pci_init(2, reg); 102 #endif 103 } 104