1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/fsl_serdes.h> 12 #include <asm/arch/soc.h> 13 #include <fdt_support.h> 14 #include <hwconfig.h> 15 #include <ahci.h> 16 #include <mmc.h> 17 #include <scsi.h> 18 #include <fm_eth.h> 19 #include <fsl_csu.h> 20 #include <fsl_esdhc.h> 21 #include <fsl_ifc.h> 22 #include <fsl_sec.h> 23 #include "cpld.h" 24 #ifdef CONFIG_U_QE 25 #include <fsl_qe.h> 26 #endif 27 #ifdef CONFIG_FSL_LS_PPA 28 #include <asm/arch/ppa.h> 29 #endif 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 int checkboard(void) 34 { 35 static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; 36 #ifndef CONFIG_SD_BOOT 37 u8 cfg_rcw_src1, cfg_rcw_src2; 38 u16 cfg_rcw_src; 39 #endif 40 u8 sd1refclk_sel; 41 42 printf("Board: LS1043ARDB, boot from "); 43 44 #ifdef CONFIG_SD_BOOT 45 puts("SD\n"); 46 #else 47 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); 48 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); 49 cpld_rev_bit(&cfg_rcw_src1); 50 cfg_rcw_src = cfg_rcw_src1; 51 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; 52 53 if (cfg_rcw_src == 0x25) 54 printf("vBank %d\n", CPLD_READ(vbank)); 55 else if (cfg_rcw_src == 0x106) 56 puts("NAND\n"); 57 else 58 printf("Invalid setting of SW4\n"); 59 #endif 60 61 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), 62 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); 63 64 puts("SERDES Reference Clocks:\n"); 65 sd1refclk_sel = CPLD_READ(sd1refclk_sel); 66 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); 67 68 return 0; 69 } 70 71 int dram_init(void) 72 { 73 gd->ram_size = initdram(0); 74 75 return 0; 76 } 77 78 int board_early_init_f(void) 79 { 80 fsl_lsch2_early_init_f(); 81 82 return 0; 83 } 84 85 int board_init(void) 86 { 87 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 88 89 #ifdef CONFIG_FSL_IFC 90 init_final_memctl_regs(); 91 #endif 92 93 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 94 enable_layerscape_ns_access(); 95 #endif 96 97 #ifdef CONFIG_FSL_LS_PPA 98 ppa_init(); 99 #endif 100 101 #ifdef CONFIG_U_QE 102 u_qe_init(); 103 #endif 104 /* invert AQR105 IRQ pins polarity */ 105 out_be32(&scfg->intpcr, AQR105_IRQ_MASK); 106 107 return 0; 108 } 109 110 int config_board_mux(void) 111 { 112 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 113 u32 usb_pwrfault; 114 115 if (hwconfig("qe-hdlc")) { 116 out_be32(&scfg->rcwpmuxcr0, 117 (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600); 118 printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n", 119 in_be32(&scfg->rcwpmuxcr0)); 120 } else { 121 #ifdef CONFIG_HAS_FSL_XHCI_USB 122 out_be32(&scfg->rcwpmuxcr0, 0x3333); 123 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); 124 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << 125 SCFG_USBPWRFAULT_USB3_SHIFT) | 126 (SCFG_USBPWRFAULT_DEDICATED << 127 SCFG_USBPWRFAULT_USB2_SHIFT) | 128 (SCFG_USBPWRFAULT_SHARED << 129 SCFG_USBPWRFAULT_USB1_SHIFT); 130 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); 131 #endif 132 } 133 return 0; 134 } 135 136 #if defined(CONFIG_MISC_INIT_R) 137 int misc_init_r(void) 138 { 139 config_board_mux(); 140 #ifdef CONFIG_SECURE_BOOT 141 /* In case of Secure Boot, the IBR configures the SMMU 142 * to allow only Secure transactions. 143 * SMMU must be reset in bypass mode. 144 * Set the ClientPD bit and Clear the USFCFG Bit 145 */ 146 u32 val; 147 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 148 out_le32(SMMU_SCR0, val); 149 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 150 out_le32(SMMU_NSCR0, val); 151 #endif 152 #ifdef CONFIG_FSL_CAAM 153 return sec_init(); 154 #endif 155 return 0; 156 } 157 #endif 158 159 void fdt_del_qe(void *blob) 160 { 161 int nodeoff = 0; 162 163 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, 164 "fsl,qe")) >= 0) { 165 fdt_del_node(blob, nodeoff); 166 } 167 } 168 169 int ft_board_setup(void *blob, bd_t *bd) 170 { 171 u64 base[CONFIG_NR_DRAM_BANKS]; 172 u64 size[CONFIG_NR_DRAM_BANKS]; 173 174 /* fixup DT for the two DDR banks */ 175 base[0] = gd->bd->bi_dram[0].start; 176 size[0] = gd->bd->bi_dram[0].size; 177 base[1] = gd->bd->bi_dram[1].start; 178 size[1] = gd->bd->bi_dram[1].size; 179 180 fdt_fixup_memory_banks(blob, base, size, 2); 181 ft_cpu_setup(blob, bd); 182 183 #ifdef CONFIG_SYS_DPAA_FMAN 184 fdt_fixup_fman_ethernet(blob); 185 #endif 186 187 /* 188 * qe-hdlc and usb multi-use the pins, 189 * when set hwconfig to qe-hdlc, delete usb node. 190 */ 191 if (hwconfig("qe-hdlc")) 192 #ifdef CONFIG_HAS_FSL_XHCI_USB 193 fdt_del_node_and_alias(blob, "usb1"); 194 #endif 195 /* 196 * qe just support qe-uart and qe-hdlc, 197 * if qe-uart and qe-hdlc are not set in hwconfig, 198 * delete qe node. 199 */ 200 if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc")) 201 fdt_del_qe(blob); 202 203 return 0; 204 } 205 206 u8 flash_read8(void *addr) 207 { 208 return __raw_readb(addr + 1); 209 } 210 211 void flash_write16(u16 val, void *addr) 212 { 213 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 214 215 __raw_writew(shftval, addr); 216 } 217 218 u16 flash_read16(void *addr) 219 { 220 u16 val = __raw_readw(addr); 221 222 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 223 } 224