1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <asm/io.h> 10 #include <asm/arch/immap_ls102xa.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/fsl_serdes.h> 13 #include <asm/arch/ls102xa_stream_id.h> 14 #include <asm/arch/ls102xa_devdis.h> 15 #include <hwconfig.h> 16 #include <mmc.h> 17 #include <fsl_csu.h> 18 #include <fsl_esdhc.h> 19 #include <fsl_ifc.h> 20 #include <fsl_sec.h> 21 #include <spl.h> 22 #include <fsl_devdis.h> 23 24 #include "../common/sleep.h" 25 #include "../common/qixis.h" 26 #include "ls1021aqds_qixis.h" 27 #ifdef CONFIG_U_QE 28 #include "../../../drivers/qe/qe.h" 29 #endif 30 31 #define PIN_MUX_SEL_CAN 0x03 32 #define PIN_MUX_SEL_IIC2 0xa0 33 #define PIN_MUX_SEL_RGMII 0x00 34 #define PIN_MUX_SEL_SAI 0x0c 35 #define PIN_MUX_SEL_SDHC 0x00 36 37 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value) 38 #define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value) 39 DECLARE_GLOBAL_DATA_PTR; 40 41 enum { 42 MUX_TYPE_CAN, 43 MUX_TYPE_IIC2, 44 MUX_TYPE_RGMII, 45 MUX_TYPE_SAI, 46 MUX_TYPE_SDHC, 47 MUX_TYPE_SD_PCI4, 48 MUX_TYPE_SD_PC_SA_SG_SG, 49 MUX_TYPE_SD_PC_SA_PC_SG, 50 MUX_TYPE_SD_PC_SG_SG, 51 }; 52 53 enum { 54 GE0_CLK125, 55 GE2_CLK125, 56 GE1_CLK125, 57 }; 58 59 int checkboard(void) 60 { 61 #ifndef CONFIG_QSPI_BOOT 62 char buf[64]; 63 #endif 64 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) 65 u8 sw; 66 #endif 67 68 puts("Board: LS1021AQDS\n"); 69 70 #ifdef CONFIG_SD_BOOT 71 puts("SD\n"); 72 #elif CONFIG_QSPI_BOOT 73 puts("QSPI\n"); 74 #else 75 sw = QIXIS_READ(brdcfg[0]); 76 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 77 78 if (sw < 0x8) 79 printf("vBank: %d\n", sw); 80 else if (sw == 0x8) 81 puts("PromJet\n"); 82 else if (sw == 0x9) 83 puts("NAND\n"); 84 else if (sw == 0x15) 85 printf("IFCCard\n"); 86 else 87 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 88 #endif 89 90 #ifndef CONFIG_QSPI_BOOT 91 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", 92 QIXIS_READ(id), QIXIS_READ(arch)); 93 94 printf("FPGA: v%d (%s), build %d\n", 95 (int)QIXIS_READ(scver), qixis_read_tag(buf), 96 (int)qixis_read_minor()); 97 #endif 98 99 return 0; 100 } 101 102 unsigned long get_board_sys_clk(void) 103 { 104 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 105 106 switch (sysclk_conf & 0x0f) { 107 case QIXIS_SYSCLK_64: 108 return 64000000; 109 case QIXIS_SYSCLK_83: 110 return 83333333; 111 case QIXIS_SYSCLK_100: 112 return 100000000; 113 case QIXIS_SYSCLK_125: 114 return 125000000; 115 case QIXIS_SYSCLK_133: 116 return 133333333; 117 case QIXIS_SYSCLK_150: 118 return 150000000; 119 case QIXIS_SYSCLK_160: 120 return 160000000; 121 case QIXIS_SYSCLK_166: 122 return 166666666; 123 } 124 return 66666666; 125 } 126 127 unsigned long get_board_ddr_clk(void) 128 { 129 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 130 131 switch ((ddrclk_conf & 0x30) >> 4) { 132 case QIXIS_DDRCLK_100: 133 return 100000000; 134 case QIXIS_DDRCLK_125: 135 return 125000000; 136 case QIXIS_DDRCLK_133: 137 return 133333333; 138 } 139 return 66666666; 140 } 141 142 unsigned int get_soc_major_rev(void) 143 { 144 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 145 unsigned int svr, major; 146 147 svr = in_be32(&gur->svr); 148 major = SVR_MAJ(svr); 149 150 return major; 151 } 152 153 int select_i2c_ch_pca9547(u8 ch) 154 { 155 int ret; 156 157 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 158 if (ret) { 159 puts("PCA: failed to select proper channel\n"); 160 return ret; 161 } 162 163 return 0; 164 } 165 166 int dram_init(void) 167 { 168 /* 169 * When resuming from deep sleep, the I2C channel may not be 170 * in the default channel. So, switch to the default channel 171 * before accessing DDR SPD. 172 */ 173 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 174 gd->ram_size = initdram(0); 175 176 return 0; 177 } 178 179 #ifdef CONFIG_FSL_ESDHC 180 struct fsl_esdhc_cfg esdhc_cfg[1] = { 181 {CONFIG_SYS_FSL_ESDHC_ADDR}, 182 }; 183 184 int board_mmc_init(bd_t *bis) 185 { 186 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 187 188 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 189 } 190 #endif 191 192 int board_early_init_f(void) 193 { 194 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 195 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 196 unsigned int major; 197 198 #ifdef CONFIG_TSEC_ENET 199 /* clear BD & FR bits for BE BD's and frame data */ 200 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); 201 #endif 202 203 #ifdef CONFIG_FSL_IFC 204 init_early_memctl_regs(); 205 #endif 206 207 #ifdef CONFIG_FSL_QSPI 208 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); 209 #endif 210 211 #ifdef CONFIG_FSL_DCU_FB 212 out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); 213 #endif 214 215 /* Configure Little endian for SAI, ASRC and SPDIF */ 216 out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); 217 218 /* 219 * Enable snoop requests and DVM message requests for 220 * Slave insterface S4 (A7 core cluster) 221 */ 222 out_le32(&cci->slave[4].snoop_ctrl, 223 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); 224 225 major = get_soc_major_rev(); 226 if (major == SOC_MAJOR_VER_1_0) { 227 /* 228 * Set CCI-400 Slave interface S1, S2 Shareable Override 229 * Register All transactions are treated as non-shareable 230 */ 231 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 232 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 233 234 /* Workaround for the issue that DDR could not respond to 235 * barrier transaction which is generated by executing DSB/ISB 236 * instruction. Set CCI-400 control override register to 237 * terminate the barrier transaction. After DDR is initialized, 238 * allow barrier transaction to DDR again */ 239 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); 240 } 241 242 #if defined(CONFIG_DEEP_SLEEP) 243 if (is_warm_boot()) 244 fsl_dp_disable_console(); 245 #endif 246 247 return 0; 248 } 249 250 #ifdef CONFIG_SPL_BUILD 251 void board_init_f(ulong dummy) 252 { 253 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 254 unsigned int major; 255 256 #ifdef CONFIG_NAND_BOOT 257 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 258 u32 porsr1, pinctl; 259 260 /* 261 * There is LS1 SoC issue where NOR, FPGA are inaccessible during 262 * NAND boot because IFC signals > IFC_AD7 are not enabled. 263 * This workaround changes RCW source to make all signals enabled. 264 */ 265 porsr1 = in_be32(&gur->porsr1); 266 pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) | 267 DCFG_CCSR_PORSR1_RCW_SRC_I2C); 268 out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), 269 pinctl); 270 #endif 271 272 /* Clear the BSS */ 273 memset(__bss_start, 0, __bss_end - __bss_start); 274 275 #ifdef CONFIG_FSL_IFC 276 init_early_memctl_regs(); 277 #endif 278 279 get_clocks(); 280 281 #if defined(CONFIG_DEEP_SLEEP) 282 if (is_warm_boot()) 283 fsl_dp_disable_console(); 284 #endif 285 286 preloader_console_init(); 287 288 #ifdef CONFIG_SPL_I2C_SUPPORT 289 i2c_init_all(); 290 #endif 291 292 major = get_soc_major_rev(); 293 if (major == SOC_MAJOR_VER_1_0) 294 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); 295 296 dram_init(); 297 298 /* Allow OCRAM access permission as R/W */ 299 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 300 enable_layerscape_ns_access(); 301 #endif 302 303 board_init_r(NULL, 0); 304 } 305 #endif 306 307 void config_etseccm_source(int etsec_gtx_125_mux) 308 { 309 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 310 311 switch (etsec_gtx_125_mux) { 312 case GE0_CLK125: 313 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125); 314 debug("etseccm set to GE0_CLK125\n"); 315 break; 316 317 case GE2_CLK125: 318 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); 319 debug("etseccm set to GE2_CLK125\n"); 320 break; 321 322 case GE1_CLK125: 323 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125); 324 debug("etseccm set to GE1_CLK125\n"); 325 break; 326 327 default: 328 printf("Error! trying to set etseccm to invalid value\n"); 329 break; 330 } 331 } 332 333 int config_board_mux(int ctrl_type) 334 { 335 u8 reg12, reg14; 336 337 reg12 = QIXIS_READ(brdcfg[12]); 338 reg14 = QIXIS_READ(brdcfg[14]); 339 340 switch (ctrl_type) { 341 case MUX_TYPE_CAN: 342 config_etseccm_source(GE2_CLK125); 343 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN); 344 break; 345 case MUX_TYPE_IIC2: 346 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2); 347 break; 348 case MUX_TYPE_RGMII: 349 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII); 350 break; 351 case MUX_TYPE_SAI: 352 config_etseccm_source(GE2_CLK125); 353 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI); 354 break; 355 case MUX_TYPE_SDHC: 356 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC); 357 break; 358 case MUX_TYPE_SD_PCI4: 359 reg12 = 0x38; 360 break; 361 case MUX_TYPE_SD_PC_SA_SG_SG: 362 reg12 = 0x01; 363 break; 364 case MUX_TYPE_SD_PC_SA_PC_SG: 365 reg12 = 0x01; 366 break; 367 case MUX_TYPE_SD_PC_SG_SG: 368 reg12 = 0x21; 369 break; 370 default: 371 printf("Wrong mux interface type\n"); 372 return -1; 373 } 374 375 QIXIS_WRITE(brdcfg[12], reg12); 376 QIXIS_WRITE(brdcfg[14], reg14); 377 378 return 0; 379 } 380 381 int config_serdes_mux(void) 382 { 383 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR; 384 u32 cfg; 385 386 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; 387 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; 388 389 switch (cfg) { 390 case 0x0: 391 config_board_mux(MUX_TYPE_SD_PCI4); 392 break; 393 case 0x30: 394 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG); 395 break; 396 case 0x60: 397 config_board_mux(MUX_TYPE_SD_PC_SG_SG); 398 break; 399 case 0x70: 400 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG); 401 break; 402 default: 403 printf("SRDS1 prtcl:0x%x\n", cfg); 404 break; 405 } 406 407 return 0; 408 } 409 410 int misc_init_r(void) 411 { 412 int conflict_flag; 413 414 /* some signals can not enable simultaneous*/ 415 conflict_flag = 0; 416 if (hwconfig("sdhc")) 417 conflict_flag++; 418 if (hwconfig("iic2")) 419 conflict_flag++; 420 if (conflict_flag > 1) { 421 printf("WARNING: pin conflict !\n"); 422 return 0; 423 } 424 425 conflict_flag = 0; 426 if (hwconfig("rgmii")) 427 conflict_flag++; 428 if (hwconfig("can")) 429 conflict_flag++; 430 if (hwconfig("sai")) 431 conflict_flag++; 432 if (conflict_flag > 1) { 433 printf("WARNING: pin conflict !\n"); 434 return 0; 435 } 436 437 if (hwconfig("can")) 438 config_board_mux(MUX_TYPE_CAN); 439 else if (hwconfig("rgmii")) 440 config_board_mux(MUX_TYPE_RGMII); 441 else if (hwconfig("sai")) 442 config_board_mux(MUX_TYPE_SAI); 443 444 if (hwconfig("iic2")) 445 config_board_mux(MUX_TYPE_IIC2); 446 else if (hwconfig("sdhc")) 447 config_board_mux(MUX_TYPE_SDHC); 448 449 #ifdef CONFIG_FSL_DEVICE_DISABLE 450 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); 451 #endif 452 #ifdef CONFIG_FSL_CAAM 453 return sec_init(); 454 #endif 455 return 0; 456 } 457 458 struct liodn_id_table sec_liodn_tbl[] = { 459 SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10), 460 SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10), 461 SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10), 462 SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10), 463 SET_SEC_RTIC_LIODN_ENTRY(a, 0x10), 464 SET_SEC_RTIC_LIODN_ENTRY(b, 0x10), 465 SET_SEC_RTIC_LIODN_ENTRY(c, 0x10), 466 SET_SEC_RTIC_LIODN_ENTRY(d, 0x10), 467 SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10), 468 SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10), 469 SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10), 470 SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10), 471 SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10), 472 SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10), 473 SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10), 474 SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10), 475 }; 476 477 struct smmu_stream_id dev_stream_id[] = { 478 { 0x100, 0x01, "ETSEC MAC1" }, 479 { 0x104, 0x02, "ETSEC MAC2" }, 480 { 0x108, 0x03, "ETSEC MAC3" }, 481 { 0x10c, 0x04, "PEX1" }, 482 { 0x110, 0x05, "PEX2" }, 483 { 0x114, 0x06, "qDMA" }, 484 { 0x118, 0x07, "SATA" }, 485 { 0x11c, 0x08, "USB3" }, 486 { 0x120, 0x09, "QE" }, 487 { 0x124, 0x0a, "eSDHC" }, 488 { 0x128, 0x0b, "eMA" }, 489 { 0x14c, 0x0c, "2D-ACE" }, 490 { 0x150, 0x0d, "USB2" }, 491 { 0x18c, 0x0e, "DEBUG" }, 492 }; 493 494 int board_init(void) 495 { 496 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 497 unsigned int major; 498 499 major = get_soc_major_rev(); 500 if (major == SOC_MAJOR_VER_1_0) { 501 /* Set CCI-400 control override register to 502 * enable barrier transaction */ 503 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 504 } 505 506 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 507 508 #ifndef CONFIG_SYS_FSL_NO_SERDES 509 fsl_serdes_init(); 510 config_serdes_mux(); 511 #endif 512 513 ls1021x_config_caam_stream_id(sec_liodn_tbl, 514 ARRAY_SIZE(sec_liodn_tbl)); 515 ls102xa_config_smmu_stream_id(dev_stream_id, 516 ARRAY_SIZE(dev_stream_id)); 517 518 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 519 enable_layerscape_ns_access(); 520 #endif 521 522 #ifdef CONFIG_U_QE 523 u_qe_init(); 524 #endif 525 526 return 0; 527 } 528 529 #if defined(CONFIG_DEEP_SLEEP) 530 void board_sleep_prepare(void) 531 { 532 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; 533 unsigned int major; 534 535 major = get_soc_major_rev(); 536 if (major == SOC_MAJOR_VER_1_0) { 537 /* Set CCI-400 control override register to 538 * enable barrier transaction */ 539 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 540 } 541 542 543 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 544 enable_layerscape_ns_access(); 545 #endif 546 } 547 #endif 548 549 int ft_board_setup(void *blob, bd_t *bd) 550 { 551 ft_cpu_setup(blob, bd); 552 553 #ifdef CONFIG_PCI 554 ft_pci_setup(blob, bd); 555 #endif 556 557 return 0; 558 } 559 560 u8 flash_read8(void *addr) 561 { 562 return __raw_readb(addr + 1); 563 } 564 565 void flash_write16(u16 val, void *addr) 566 { 567 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 568 569 __raw_writew(shftval, addr); 570 } 571 572 u16 flash_read16(void *addr) 573 { 574 u16 val = __raw_readw(addr); 575 576 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 577 } 578