1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2018 NXP
4 */
5
6 #include <common.h>
7 #include <malloc.h>
8 #include <errno.h>
9 #include <asm/io.h>
10 #include <miiphy.h>
11 #include <netdev.h>
12 #include <asm/mach-imx/iomux-v3.h>
13 #include <asm-generic/gpio.h>
14 #include <fsl_esdhc.h>
15 #include <mmc.h>
16 #include <asm/arch/imx8mq_pins.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/mach-imx/gpio.h>
19 #include <asm/mach-imx/mxc_i2c.h>
20 #include <asm/arch/clock.h>
21 #include <spl.h>
22 #include <power/pmic.h>
23 #include <power/pfuze100_pmic.h>
24 #include "../common/pfuze.h"
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
29
30 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
31
32 static iomux_v3_cfg_t const wdog_pads[] = {
33 IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
34 };
35
36 static iomux_v3_cfg_t const uart_pads[] = {
37 IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
38 IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
39 };
40
board_early_init_f(void)41 int board_early_init_f(void)
42 {
43 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
44
45 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
46 set_wdog_reset(wdog);
47
48 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
49
50 return 0;
51 }
52
dram_init(void)53 int dram_init(void)
54 {
55 /* rom_pointer[1] contains the size of TEE occupies */
56 if (rom_pointer[1])
57 gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
58 else
59 gd->ram_size = PHYS_SDRAM_SIZE;
60
61 return 0;
62 }
63
64 #ifdef CONFIG_FEC_MXC
65 #define FEC_RST_PAD IMX_GPIO_NR(1, 9)
66 static iomux_v3_cfg_t const fec1_rst_pads[] = {
67 IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
68 };
69
setup_iomux_fec(void)70 static void setup_iomux_fec(void)
71 {
72 imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
73 ARRAY_SIZE(fec1_rst_pads));
74
75 gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
76 gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
77 udelay(500);
78 gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
79 }
80
setup_fec(void)81 static int setup_fec(void)
82 {
83 struct iomuxc_gpr_base_regs *gpr =
84 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
85
86 setup_iomux_fec();
87
88 /* Use 125M anatop REF_CLK1 for ENET1, not from external */
89 clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
90 return set_clk_enet(ENET_125MHZ);
91 }
92
board_phy_config(struct phy_device * phydev)93 int board_phy_config(struct phy_device *phydev)
94 {
95 /* enable rgmii rxc skew and phy mode select to RGMII copper */
96 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
97 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
98
99 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
100 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
101
102 if (phydev->drv->config)
103 phydev->drv->config(phydev);
104 return 0;
105 }
106 #endif
107
board_init(void)108 int board_init(void)
109 {
110 #ifdef CONFIG_FEC_MXC
111 setup_fec();
112 #endif
113
114 return 0;
115 }
116
board_mmc_get_env_dev(int devno)117 int board_mmc_get_env_dev(int devno)
118 {
119 return devno;
120 }
121
board_late_init(void)122 int board_late_init(void)
123 {
124 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
125 env_set("board_name", "EVK");
126 env_set("board_rev", "iMX8MQ");
127 #endif
128
129 return 0;
130 }
131