1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 241d91011SPrabhakar Kushwaha /* 341d91011SPrabhakar Kushwaha * Copyright 2013 Freescale Semiconductor, Inc. 441d91011SPrabhakar Kushwaha */ 541d91011SPrabhakar Kushwaha 641d91011SPrabhakar Kushwaha #include <common.h> 741d91011SPrabhakar Kushwaha #include <asm/fsl_law.h> 841d91011SPrabhakar Kushwaha #include <asm/mmu.h> 941d91011SPrabhakar Kushwaha 1041d91011SPrabhakar Kushwaha struct law_entry law_table[] = { 1141d91011SPrabhakar Kushwaha SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_IFC), 1283e0c2bbSPrabhakar Kushwaha #ifdef CONFIG_SYS_NAND_BASE_PHYS 1341d91011SPrabhakar Kushwaha SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), 1483e0c2bbSPrabhakar Kushwaha #endif 1583e0c2bbSPrabhakar Kushwaha #ifdef CONFIG_SYS_FPGA_BASE_PHYS 1641d91011SPrabhakar Kushwaha SET_LAW(CONFIG_SYS_FPGA_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), 1783e0c2bbSPrabhakar Kushwaha #endif 1864501c66SPriyanka Jain SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M, 1964501c66SPriyanka Jain LAW_TRGT_IF_DSP_CCSR), 2064501c66SPriyanka Jain SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_32M, 2164501c66SPriyanka Jain LAW_TRGT_IF_OCN_DSP), 2264501c66SPriyanka Jain SET_LAW(CONFIG_SYS_FSL_DSP_M3_RAM_ADDR, LAW_SIZE_32K, 2364501c66SPriyanka Jain LAW_TRGT_IF_CLASS_DSP), 2464501c66SPriyanka Jain SET_LAW(CONFIG_SYS_FSL_DSP_DDR_ADDR, LAW_SIZE_1G, 2564501c66SPriyanka Jain LAW_TRGT_IF_CLASS_DSP) 2641d91011SPrabhakar Kushwaha }; 2741d91011SPrabhakar Kushwaha 2841d91011SPrabhakar Kushwaha int num_law_entries = ARRAY_SIZE(law_table); 29