1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/mmu.h> 9 #include <asm/immap_85xx.h> 10 #include <asm/processor.h> 11 #include <fsl_ddr_sdram.h> 12 #include <fsl_ddr_dimm_params.h> 13 #include <asm/io.h> 14 #include <asm/fsl_law.h> 15 16 #ifndef CONFIG_SYS_DDR_RAW_TIMING 17 #define CONFIG_SYS_DRAM_SIZE 1024 18 19 fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { 20 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, 21 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, 22 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, 23 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, 24 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, 25 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, 26 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, 27 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, 28 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, 29 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, 30 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, 31 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, 32 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, 33 .ddr_data_init = CONFIG_MEM_INIT_VALUE, 34 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, 35 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, 36 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, 37 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, 38 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, 39 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, 40 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800, 41 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, 42 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, 43 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 44 }; 45 46 fixed_ddr_parm_t fixed_ddr_parm_0[] = { 47 {750, 850, &ddr_cfg_regs_800}, 48 {0, 0, NULL} 49 }; 50 51 unsigned long get_sdram_size(void) 52 { 53 return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DRAM_SIZE); 54 } 55 56 /* 57 * Fixed sdram init -- doesn't use serial presence detect. 58 */ 59 phys_size_t fixed_sdram(void) 60 { 61 int i; 62 char buf[32]; 63 fsl_ddr_cfg_regs_t ddr_cfg_regs; 64 phys_size_t ddr_size; 65 ulong ddr_freq, ddr_freq_mhz; 66 67 ddr_freq = get_ddr_freq(0); 68 ddr_freq_mhz = ddr_freq / 1000000; 69 70 printf("Configuring DDR for %s MT/s data rate\n", 71 strmhz(buf, ddr_freq)); 72 73 for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { 74 if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && 75 (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { 76 memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings, 77 sizeof(ddr_cfg_regs)); 78 break; 79 } 80 } 81 82 if (fixed_ddr_parm_0[i].max_freq == 0) { 83 panic("Unsupported DDR data rate %s MT/s data rate\n", 84 strmhz(buf, ddr_freq)); 85 } 86 87 ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 88 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); 89 90 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, 91 LAW_TRGT_IF_DDR_1) < 0) { 92 printf("ERROR setting Local Access Windows for DDR\n"); 93 return 0; 94 } 95 96 return ddr_size; 97 } 98 99 #else /* CONFIG_SYS_DDR_RAW_TIMING */ 100 /* Micron MT41J256M8HX-15E */ 101 dimm_params_t ddr_raw_timing = { 102 .n_ranks = 1, 103 .rank_density = 1073741824u, 104 .capacity = 1073741824u, 105 .primary_sdram_width = 32, 106 .ec_sdram_width = 0, 107 .registered_dimm = 0, 108 .mirrored_dimm = 0, 109 .n_row_addr = 15, 110 .n_col_addr = 10, 111 .n_banks_per_sdram_device = 8, 112 .edc_config = 0, 113 .burst_lengths_bitmask = 0x0c, 114 115 .tckmin_x_ps = 1870, 116 .caslat_x = 0x1e << 4, /* 5,6,7,8 */ 117 .taa_ps = 13125, 118 .twr_ps = 15000, 119 .trcd_ps = 13125, 120 .trrd_ps = 7500, 121 .trp_ps = 13125, 122 .tras_ps = 37500, 123 .trc_ps = 50625, 124 .trfc_ps = 160000, 125 .twtr_ps = 7500, 126 .trtp_ps = 7500, 127 .refresh_rate_ps = 7800000, 128 .tfaw_ps = 37500, 129 }; 130 131 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 132 unsigned int controller_number, 133 unsigned int dimm_number) 134 { 135 const char dimm_model[] = "Fixed DDR on board"; 136 137 if ((controller_number == 0) && (dimm_number == 0)) { 138 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); 139 memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); 140 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); 141 } 142 143 return 0; 144 } 145 146 void fsl_ddr_board_options(memctl_options_t *popts, 147 dimm_params_t *pdimm, 148 unsigned int ctrl_num) 149 { 150 int i; 151 popts->clk_adjust = 6; 152 popts->cpo_override = 0x1f; 153 popts->write_data_delay = 2; 154 popts->half_strength_driver_enable = 1; 155 /* Write leveling override */ 156 popts->wrlvl_en = 1; 157 popts->wrlvl_override = 1; 158 popts->wrlvl_sample = 0xf; 159 popts->wrlvl_start = 0x8; 160 popts->trwt_override = 1; 161 popts->trwt = 0; 162 163 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 164 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; 165 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; 166 } 167 } 168 169 #endif /* CONFIG_SYS_DDR_RAW_TIMING */ 170