xref: /openbmc/u-boot/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c (revision 83d290c56fab2d38cd1ab4c4cc7099559c1d5046)
1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
282ceba2cSStefan Roese /*
382ceba2cSStefan Roese  * Copyright (C) 2016 Stefan Roese <sr@denx.de>
482ceba2cSStefan Roese  */
582ceba2cSStefan Roese 
682ceba2cSStefan Roese #include <common.h>
7303dfc2eSStefan Roese #include <i2c.h>
882ceba2cSStefan Roese #include <winbond_w83627.h>
982ceba2cSStefan Roese #include <asm/gpio.h>
1082ceba2cSStefan Roese #include <asm/ibmpc.h>
1182ceba2cSStefan Roese #include <asm/pnp_def.h>
1282ceba2cSStefan Roese 
board_early_init_f(void)1382ceba2cSStefan Roese int board_early_init_f(void)
1482ceba2cSStefan Roese {
15f2a751beSStefan Roese #ifndef CONFIG_INTERNAL_UART
1682ceba2cSStefan Roese 	/*
1782ceba2cSStefan Roese 	 * The FSP enables the BayTrail internal legacy UART (again).
1882ceba2cSStefan Roese 	 * Disable it again, so that the Winbond one can be used.
1982ceba2cSStefan Roese 	 */
2082ceba2cSStefan Roese 	setup_internal_uart(0);
2182ceba2cSStefan Roese 
2282ceba2cSStefan Roese 	/* Enable the legacy UART in the Winbond W83627 Super IO chip */
2382ceba2cSStefan Roese 	winbond_enable_serial(PNP_DEV(WINBOND_IO_PORT, W83627DHG_SP1),
2482ceba2cSStefan Roese 			      UART0_BASE, UART0_IRQ);
25f2a751beSStefan Roese #endif
2682ceba2cSStefan Roese 
2782ceba2cSStefan Roese 	return 0;
2882ceba2cSStefan Roese }
2982ceba2cSStefan Roese 
board_late_init(void)30303dfc2eSStefan Roese int board_late_init(void)
31303dfc2eSStefan Roese {
32303dfc2eSStefan Roese 	struct udevice *dev;
33303dfc2eSStefan Roese 	u8 buf[8];
34303dfc2eSStefan Roese 	int ret;
35303dfc2eSStefan Roese 
36303dfc2eSStefan Roese 	/* Configure SMSC USB2513 USB Hub: 7bit address 0x2c */
37303dfc2eSStefan Roese 	ret = i2c_get_chip_for_busnum(0, 0x2c, 1, &dev);
38303dfc2eSStefan Roese 	if (ret) {
39303dfc2eSStefan Roese 		printf("Cannot find USB2513: %d\n", ret);
40303dfc2eSStefan Roese 		return 0;
41303dfc2eSStefan Roese 	}
42303dfc2eSStefan Roese 
43303dfc2eSStefan Roese 	/*
44303dfc2eSStefan Roese 	 * The first access to the USB Hub fails sometimes, so lets read
45303dfc2eSStefan Roese 	 * a dummy byte to be sure here
46303dfc2eSStefan Roese 	 */
47303dfc2eSStefan Roese 	dm_i2c_read(dev, 0x00, buf, 1);
48303dfc2eSStefan Roese 
49303dfc2eSStefan Roese 	/*
50303dfc2eSStefan Roese 	 * The SMSC hub is not visible on the I2C bus after the first
51303dfc2eSStefan Roese 	 * configuration at power-up. The following code deliberately
52303dfc2eSStefan Roese 	 * does not report upon failure of these I2C write calls.
53303dfc2eSStefan Roese 	 */
54303dfc2eSStefan Roese 	buf[0] = 0x93;
55303dfc2eSStefan Roese 	dm_i2c_write(dev, 0x06, buf, 1);
56303dfc2eSStefan Roese 
57303dfc2eSStefan Roese 	buf[0] = 0xaa;
58303dfc2eSStefan Roese 	dm_i2c_write(dev, 0xf8, buf, 1);
59303dfc2eSStefan Roese 
60303dfc2eSStefan Roese 	buf[0] = 0x0f;
61303dfc2eSStefan Roese 	dm_i2c_write(dev, 0xfa, buf, 1);
62303dfc2eSStefan Roese 
63303dfc2eSStefan Roese 	buf[0] = 0x01;
64303dfc2eSStefan Roese 	dm_i2c_write(dev, 0xff, buf, 1);
65303dfc2eSStefan Roese 
66303dfc2eSStefan Roese 	return 0;
67303dfc2eSStefan Roese }
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