1 /* 2 * Board functions for Compulab CM-T335 board 3 * 4 * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ 5 * 6 * Author: Ilya Ledvich <ilya@compulab.co.il> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <errno.h> 13 #include <miiphy.h> 14 #include <cpsw.h> 15 16 #include <asm/arch/sys_proto.h> 17 #include <asm/arch/hardware_am33xx.h> 18 #include <asm/io.h> 19 #include <asm/gpio.h> 20 21 #include "../common/eeprom.h" 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 /* 26 * Basic board specific setup. Pinmux has been handled already. 27 */ 28 int board_init(void) 29 { 30 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 31 32 gpmc_init(); 33 34 return 0; 35 } 36 37 #if defined (CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD) 38 static void cpsw_control(int enabled) 39 { 40 /* VTP can be added here */ 41 return; 42 } 43 44 static struct cpsw_slave_data cpsw_slave = { 45 .slave_reg_ofs = 0x208, 46 .sliver_reg_ofs = 0xd80, 47 .phy_id = 0, 48 .phy_if = PHY_INTERFACE_MODE_RGMII, 49 }; 50 51 static struct cpsw_platform_data cpsw_data = { 52 .mdio_base = CPSW_MDIO_BASE, 53 .cpsw_base = CPSW_BASE, 54 .mdio_div = 0xff, 55 .channels = 8, 56 .cpdma_reg_ofs = 0x800, 57 .slaves = 1, 58 .slave_data = &cpsw_slave, 59 .ale_reg_ofs = 0xd00, 60 .ale_entries = 1024, 61 .host_port_reg_ofs = 0x108, 62 .hw_stats_reg_ofs = 0x900, 63 .bd_ram_ofs = 0x2000, 64 .mac_control = (1 << 5), 65 .control = cpsw_control, 66 .host_port_num = 0, 67 .version = CPSW_CTRL_VERSION_2, 68 }; 69 70 /* PHY reset GPIO */ 71 #define GPIO_PHY_RST GPIO_PIN(3, 7) 72 73 static void board_phy_init(void) 74 { 75 gpio_request(GPIO_PHY_RST, "phy_rst"); 76 gpio_direction_output(GPIO_PHY_RST, 0); 77 mdelay(2); 78 gpio_set_value(GPIO_PHY_RST, 1); 79 mdelay(2); 80 } 81 82 static void get_efuse_mac_addr(uchar *enetaddr) 83 { 84 uint32_t mac_hi, mac_lo; 85 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 86 87 mac_lo = readl(&cdev->macid0l); 88 mac_hi = readl(&cdev->macid0h); 89 enetaddr[0] = mac_hi & 0xFF; 90 enetaddr[1] = (mac_hi & 0xFF00) >> 8; 91 enetaddr[2] = (mac_hi & 0xFF0000) >> 16; 92 enetaddr[3] = (mac_hi & 0xFF000000) >> 24; 93 enetaddr[4] = mac_lo & 0xFF; 94 enetaddr[5] = (mac_lo & 0xFF00) >> 8; 95 } 96 97 /* 98 * Routine: handle_mac_address 99 * Description: prepare MAC address for on-board Ethernet. 100 */ 101 static int handle_mac_address(void) 102 { 103 uchar enetaddr[6]; 104 int rv; 105 106 rv = eth_getenv_enetaddr("ethaddr", enetaddr); 107 if (rv) 108 return 0; 109 110 rv = cl_eeprom_read_mac_addr(enetaddr); 111 if (rv) 112 get_efuse_mac_addr(enetaddr); 113 114 if (!is_valid_ether_addr(enetaddr)) 115 return -1; 116 117 return eth_setenv_enetaddr("ethaddr", enetaddr); 118 } 119 120 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d 121 #define AR8051_PHY_DEBUG_DATA_REG 0x1e 122 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 123 #define AR8051_RGMII_TX_CLK_DLY 0x100 124 125 int board_eth_init(bd_t *bis) 126 { 127 int rv, n = 0; 128 const char *devname; 129 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 130 131 rv = handle_mac_address(); 132 if (rv) 133 printf("No MAC address found!\n"); 134 135 writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel); 136 137 board_phy_init(); 138 139 rv = cpsw_register(&cpsw_data); 140 if (rv < 0) 141 printf("Error %d registering CPSW switch\n", rv); 142 else 143 n += rv; 144 145 /* 146 * CPSW RGMII Internal Delay Mode is not supported in all PVT 147 * operating points. So we must set the TX clock delay feature 148 * in the AR8051 PHY. Since we only support a single ethernet 149 * device, we only do this for the first instance. 150 */ 151 devname = miiphy_get_current_dev(); 152 153 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, 154 AR8051_DEBUG_RGMII_CLK_DLY_REG); 155 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, 156 AR8051_RGMII_TX_CLK_DLY); 157 return n; 158 } 159 #endif /* CONFIG_DRIVER_TI_CPSW && !CONFIG_SPL_BUILD */ 160