1 /* 2 * (C) Copyright 2002 3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 4 * Marius Groeger <mgroeger@sysgo.de> 5 * 6 * (C) Copyright 2002 7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> 8 * 9 * (C) Copyright 2003 10 * Texas Instruments, <www.ti.com> 11 * Kshitij Gupta <Kshitij@ti.com> 12 * 13 * (C) Copyright 2004 14 * ARM Ltd. 15 * Philippe Robin, <philippe.robin@arm.com> 16 * 17 * SPDX-License-Identifier: GPL-2.0+ 18 */ 19 #include <common.h> 20 #include <malloc.h> 21 #include <errno.h> 22 #include <netdev.h> 23 #include <asm/io.h> 24 #include <asm/arch/systimer.h> 25 #include <asm/arch/sysctrl.h> 26 #include <asm/arch/wdt.h> 27 #include "../drivers/mmc/arm_pl180_mmci.h" 28 29 static ulong timestamp; 30 static ulong lastdec; 31 32 static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01; 33 static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE; 34 35 static void flash__init(void); 36 static void vexpress_timer_init(void); 37 DECLARE_GLOBAL_DATA_PTR; 38 39 #if defined(CONFIG_SHOW_BOOT_PROGRESS) 40 void show_boot_progress(int progress) 41 { 42 printf("Boot reached stage %d\n", progress); 43 } 44 #endif 45 46 static inline void delay(ulong loops) 47 { 48 __asm__ volatile ("1:\n" 49 "subs %0, %1, #1\n" 50 "bne 1b" : "=r" (loops) : "0" (loops)); 51 } 52 53 int board_init(void) 54 { 55 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; 56 gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS; 57 gd->flags = 0; 58 59 icache_enable(); 60 flash__init(); 61 vexpress_timer_init(); 62 63 return 0; 64 } 65 66 int board_eth_init(bd_t *bis) 67 { 68 int rc = 0; 69 #ifdef CONFIG_SMC911X 70 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 71 #endif 72 return rc; 73 } 74 75 int cpu_mmc_init(bd_t *bis) 76 { 77 int rc = 0; 78 (void) bis; 79 #ifdef CONFIG_ARM_PL180_MMCI 80 struct pl180_mmc_host *host; 81 82 host = malloc(sizeof(struct pl180_mmc_host)); 83 if (!host) 84 return -ENOMEM; 85 memset(host, 0, sizeof(*host)); 86 87 strcpy(host->name, "MMC"); 88 host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE; 89 host->pwr_init = INIT_PWR; 90 host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN; 91 host->voltages = VOLTAGE_WINDOW_MMC; 92 host->caps = 0; 93 host->clock_in = ARM_MCLK; 94 host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1)); 95 host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ; 96 rc = arm_pl180_mmci_init(host); 97 #endif 98 return rc; 99 } 100 101 static void flash__init(void) 102 { 103 /* Setup the sytem control register to allow writing to flash */ 104 writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN, 105 &sysctrl_base->scflashctrl); 106 } 107 108 int dram_init(void) 109 { 110 gd->ram_size = 111 get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); 112 return 0; 113 } 114 115 void dram_init_banksize(void) 116 { 117 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 118 gd->bd->bi_dram[0].size = 119 get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 120 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 121 gd->bd->bi_dram[1].size = 122 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); 123 } 124 125 int timer_init(void) 126 { 127 return 0; 128 } 129 130 /* 131 * Start timer: 132 * Setup a 32 bit timer, running at 1KHz 133 * Versatile Express Motherboard provides 1 MHz timer 134 */ 135 static void vexpress_timer_init(void) 136 { 137 /* 138 * Set clock frequency in system controller: 139 * VEXPRESS_REFCLK is 32KHz 140 * VEXPRESS_TIMCLK is 1MHz 141 */ 142 writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL | 143 SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL | 144 readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl); 145 146 /* 147 * Set Timer0 to be: 148 * Enabled, free running, no interrupt, 32-bit, wrapping 149 */ 150 writel(SYSTIMER_RELOAD, &systimer_base->timer0load); 151 writel(SYSTIMER_RELOAD, &systimer_base->timer0value); 152 writel(SYSTIMER_EN | SYSTIMER_32BIT | 153 readl(&systimer_base->timer0control), 154 &systimer_base->timer0control); 155 156 reset_timer_masked(); 157 } 158 159 int v2m_cfg_write(u32 devfn, u32 data) 160 { 161 /* Configuration interface broken? */ 162 u32 val; 163 164 devfn |= SYS_CFG_START | SYS_CFG_WRITE; 165 166 val = readl(V2M_SYS_CFGSTAT); 167 writel(val & ~SYS_CFG_COMPLETE, V2M_SYS_CFGSTAT); 168 169 writel(data, V2M_SYS_CFGDATA); 170 writel(devfn, V2M_SYS_CFGCTRL); 171 172 do { 173 val = readl(V2M_SYS_CFGSTAT); 174 } while (val == 0); 175 176 return !!(val & SYS_CFG_ERR); 177 } 178 179 /* Use the ARM Watchdog System to cause reset */ 180 void reset_cpu(ulong addr) 181 { 182 if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0)) 183 printf("Unable to reboot\n"); 184 } 185 186 /* 187 * Delay x useconds AND perserve advance timstamp value 188 * assumes timer is ticking at 1 msec 189 */ 190 void __udelay(ulong usec) 191 { 192 ulong tmo, tmp; 193 194 tmo = usec / 1000; 195 tmp = get_timer(0); /* get current timestamp */ 196 197 /* 198 * If setting this forward will roll time stamp then 199 * reset "advancing" timestamp to 0 and set lastdec value 200 * otherwise set the advancing stamp to the wake up time 201 */ 202 if ((tmo + tmp + 1) < tmp) 203 reset_timer_masked(); 204 else 205 tmo += tmp; 206 207 while (get_timer_masked() < tmo) 208 ; /* loop till wakeup event */ 209 } 210 211 ulong get_timer(ulong base) 212 { 213 return get_timer_masked() - base; 214 } 215 216 void reset_timer_masked(void) 217 { 218 lastdec = readl(&systimer_base->timer0value) / 1000; 219 timestamp = 0; 220 } 221 222 ulong get_timer_masked(void) 223 { 224 ulong now = readl(&systimer_base->timer0value) / 1000; 225 226 if (lastdec >= now) { /* normal mode (non roll) */ 227 timestamp += lastdec - now; 228 } else { /* count down timer overflowed */ 229 /* 230 * nts = ts + ld - now 231 * ts = old stamp, ld = time before passing through - 1 232 * now = amount of time after passing though - 1 233 * nts = new "advancing time stamp" 234 */ 235 timestamp += lastdec + SYSTIMER_RELOAD - now; 236 } 237 lastdec = now; 238 239 return timestamp; 240 } 241 242 void lowlevel_init(void) 243 { 244 } 245 246 ulong get_board_rev(void){ 247 return readl((u32 *)SYS_ID); 248 } 249 250 unsigned long long get_ticks(void) 251 { 252 return get_timer(0); 253 } 254 255 ulong get_tbclk(void) 256 { 257 return (ulong)CONFIG_SYS_HZ; 258 } 259 260 #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) 261 /* Setting the address at which secondary cores start from. 262 * Versatile Express uses one address for all cores, so ignore corenr 263 */ 264 void smp_set_core_boot_addr(unsigned long addr, int corenr) 265 { 266 /* The SYSFLAGS register on VExpress needs to be cleared first 267 * by writing to the next address, since any writes to the address 268 * at offset 0 will only be ORed in 269 */ 270 writel(~0, CONFIG_SYSFLAGS_ADDR + 4); 271 writel(addr, CONFIG_SYSFLAGS_ADDR); 272 } 273 #endif 274