xref: /openbmc/u-boot/board/advantech/dms-ba16/micron-1g.cfg (revision 16f416661ec5ffa46b3f879a0b83907bbec13714)
1*ff383220SAkshay Bhat/* Calibrations */
2*ff383220SAkshay Bhat/* ZQ */
3*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MPZQHWCTRL,  0xa1390003
4*ff383220SAkshay Bhat/* write leveling */
5*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
6*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
7*ff383220SAkshay BhatDATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
8*ff383220SAkshay BhatDATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
9*ff383220SAkshay Bhat/* Read DQS Gating calibration */
10*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MPDGCTRL0,   0x43480350
11*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MPDGCTRL1,   0x033C0340
12*ff383220SAkshay BhatDATA 4, MX6_MMDC_P1_MPDGCTRL0,   0x43480350
13*ff383220SAkshay BhatDATA 4, MX6_MMDC_P1_MPDGCTRL1,   0x03340314
14*ff383220SAkshay Bhat/* Read calibration */
15*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MPRDDLCTL,   0x382E2C32
16*ff383220SAkshay BhatDATA 4, MX6_MMDC_P1_MPRDDLCTL,   0x38363044
17*ff383220SAkshay Bhat/* Write calibration */
18*ff383220SAkshay BhatDATA 4 MX6_MMDC_P0_MPWRDLCTL,    0x3A38403A
19*ff383220SAkshay BhatDATA 4 MX6_MMDC_P1_MPWRDLCTL,    0x4432483E
20*ff383220SAkshay Bhat/* read data bit delay */
21*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
22*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
23*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
24*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
25*ff383220SAkshay BhatDATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
26*ff383220SAkshay BhatDATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
27*ff383220SAkshay BhatDATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
28*ff383220SAkshay BhatDATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
29*ff383220SAkshay Bhat
30*ff383220SAkshay Bhat/* Complete calibration by forced measurment */
31*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MPMUR0,	0x00000800
32*ff383220SAkshay BhatDATA 4, MX6_MMDC_P1_MPMUR0,	0x00000800
33*ff383220SAkshay Bhat
34*ff383220SAkshay Bhat/* MMDC init */
35*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MDPDC,      0x00020036
36*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MDOTC,      0x09444040
37*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MDCFG0,     0x555A79A5
38*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MDCFG1,     0xDB538E64
39*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MDCFG2,     0x01ff00db
40*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MDMISC,     0x00001740
41*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MDSCR,      0x00008000
42*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MDRWD,      0x000026d2
43*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MDOR,       0x005a1023
44*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MDASP,      0x00000027
45*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MDCTL,      0x831a0000
46*ff383220SAkshay Bhat
47*ff383220SAkshay Bhat/* Initialize memory */
48*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MDSCR,      0x04088032
49*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MDSCR,      0x0408803a
50*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MDSCR,      0x00008033
51*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MDSCR,      0x0000803b
52*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MDSCR,      0x00048031
53*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MDSCR,      0x00048039
54*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MDSCR,      0x09408030
55*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MDSCR,      0x09408038
56*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MDSCR,      0x04008040
57*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MDSCR,      0x04008048
58*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MDREF,      0x00005800
59*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MPODTCTRL,  0x00033337
60*ff383220SAkshay BhatDATA 4, MX6_MMDC_P1_MPODTCTRL,  0x00033337
61*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MDPDC,      0x00025576
62*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MAPSR,      0x00011006
63*ff383220SAkshay BhatDATA 4, MX6_MMDC_P0_MDSCR,      0x00000000
64