1 /* 2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> 3 * 4 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 5 * 6 * Copyright (C) 2011, Stefano Babic <sbabic@denx.de> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <asm/io.h> 13 #include <linux/errno.h> 14 #include <asm/arch/imx-regs.h> 15 #include <asm/arch/crm_regs.h> 16 #include <asm/arch/iomux-mx35.h> 17 #include <i2c.h> 18 #include <linux/types.h> 19 #include <asm/gpio.h> 20 #include <asm/arch/sys_proto.h> 21 #include <netdev.h> 22 #include <fdt_support.h> 23 #include <mtd_node.h> 24 #include <jffs2/load_kernel.h> 25 26 #ifndef CONFIG_BOARD_EARLY_INIT_F 27 #error "CONFIG_BOARD_EARLY_INIT_F must be set for this board" 28 #endif 29 30 #define CCM_CCMR_CONFIG 0x003F4208 31 32 #define ESDCTL_DDR2_CONFIG 0x007FFC3F 33 34 static inline void dram_wait(unsigned int count) 35 { 36 volatile unsigned int wait = count; 37 38 while (wait--) 39 ; 40 } 41 42 DECLARE_GLOBAL_DATA_PTR; 43 44 int dram_init(void) 45 { 46 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, 47 PHYS_SDRAM_1_SIZE); 48 49 return 0; 50 } 51 52 static void board_setup_sdram(void) 53 { 54 struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR; 55 56 /* Initialize with default values both CSD0/1 */ 57 writel(0x2000, &esdc->esdctl0); 58 writel(0x2000, &esdc->esdctl1); 59 60 61 mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG, 62 13, 10, 2, 0x8080); 63 } 64 65 static void setup_iomux_uart3(void) 66 { 67 static const iomux_v3_cfg_t uart3_pads[] = { 68 MX35_PAD_RTS2__UART3_RXD_MUX, 69 MX35_PAD_CTS2__UART3_TXD_MUX, 70 }; 71 72 imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); 73 } 74 75 #define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE) 76 77 static void setup_iomux_i2c(void) 78 { 79 static const iomux_v3_cfg_t i2c_pads[] = { 80 NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL), 81 NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL), 82 83 NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL), 84 NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL), 85 }; 86 87 imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); 88 } 89 90 91 static void setup_iomux_spi(void) 92 { 93 static const iomux_v3_cfg_t spi_pads[] = { 94 MX35_PAD_CSPI1_MOSI__CSPI1_MOSI, 95 MX35_PAD_CSPI1_MISO__CSPI1_MISO, 96 MX35_PAD_CSPI1_SS0__CSPI1_SS0, 97 MX35_PAD_CSPI1_SS1__CSPI1_SS1, 98 MX35_PAD_CSPI1_SCLK__CSPI1_SCLK, 99 }; 100 101 imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads)); 102 } 103 104 static void setup_iomux_fec(void) 105 { 106 static const iomux_v3_cfg_t fec_pads[] = { 107 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, 108 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, 109 MX35_PAD_FEC_RX_DV__FEC_RX_DV, 110 MX35_PAD_FEC_COL__FEC_COL, 111 MX35_PAD_FEC_RDATA0__FEC_RDATA_0, 112 MX35_PAD_FEC_TDATA0__FEC_TDATA_0, 113 MX35_PAD_FEC_TX_EN__FEC_TX_EN, 114 MX35_PAD_FEC_MDC__FEC_MDC, 115 MX35_PAD_FEC_MDIO__FEC_MDIO, 116 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, 117 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, 118 MX35_PAD_FEC_CRS__FEC_CRS, 119 MX35_PAD_FEC_RDATA1__FEC_RDATA_1, 120 MX35_PAD_FEC_TDATA1__FEC_TDATA_1, 121 MX35_PAD_FEC_RDATA2__FEC_RDATA_2, 122 MX35_PAD_FEC_TDATA2__FEC_TDATA_2, 123 MX35_PAD_FEC_RDATA3__FEC_RDATA_3, 124 MX35_PAD_FEC_TDATA3__FEC_TDATA_3, 125 }; 126 127 /* setup pins for FEC */ 128 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); 129 } 130 131 int board_early_init_f(void) 132 { 133 struct ccm_regs *ccm = 134 (struct ccm_regs *)IMX_CCM_BASE; 135 136 /* setup GPIO3_1 to set HighVCore signal */ 137 imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1); 138 gpio_direction_output(65, 1); 139 140 /* initialize PLL and clock configuration */ 141 writel(CCM_CCMR_CONFIG, &ccm->ccmr); 142 143 writel(CCM_MPLL_532_HZ, &ccm->mpctl); 144 writel(CCM_PPLL_300_HZ, &ccm->ppctl); 145 146 /* Set the core to run at 532 Mhz */ 147 writel(0x00001000, &ccm->pdr0); 148 149 /* Set-up RAM */ 150 board_setup_sdram(); 151 152 /* enable clocks */ 153 writel(readl(&ccm->cgr0) | 154 MXC_CCM_CGR0_EMI_MASK | 155 MXC_CCM_CGR0_EDIO_MASK | 156 MXC_CCM_CGR0_EPIT1_MASK, 157 &ccm->cgr0); 158 159 writel(readl(&ccm->cgr1) | 160 MXC_CCM_CGR1_FEC_MASK | 161 MXC_CCM_CGR1_GPIO1_MASK | 162 MXC_CCM_CGR1_GPIO2_MASK | 163 MXC_CCM_CGR1_GPIO3_MASK | 164 MXC_CCM_CGR1_I2C1_MASK | 165 MXC_CCM_CGR1_I2C2_MASK | 166 MXC_CCM_CGR1_I2C3_MASK, 167 &ccm->cgr1); 168 169 /* Set-up NAND */ 170 __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); 171 172 /* Set pinmux for the required peripherals */ 173 setup_iomux_uart3(); 174 setup_iomux_i2c(); 175 setup_iomux_fec(); 176 setup_iomux_spi(); 177 178 return 0; 179 } 180 181 int board_init(void) 182 { 183 /* address of boot parameters */ 184 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 185 186 return 0; 187 } 188 189 u32 get_board_rev(void) 190 { 191 int rev = 0; 192 193 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; 194 } 195 196 /* 197 * called prior to booting kernel or by 'fdt boardsetup' command 198 * 199 */ 200 int ft_board_setup(void *blob, bd_t *bd) 201 { 202 struct node_info nodes[] = { 203 { "physmap-flash.0", MTD_DEV_TYPE_NOR, }, /* NOR flash */ 204 { "mxc_nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ 205 }; 206 207 if (getenv("fdt_noauto")) { 208 puts(" Skiping ft_board_setup (fdt_noauto defined)\n"); 209 return 0; 210 } 211 212 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); 213 214 return 0; 215 } 216