1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz> 4 * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz> 5 * 6 * Derived from the code for 7 * Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de> 8 */ 9 10 #include <common.h> 11 #include <environment.h> 12 #include <i2c.h> 13 #include <miiphy.h> 14 #include <netdev.h> 15 #include <asm/io.h> 16 #include <asm/arch/cpu.h> 17 #include <asm/arch/soc.h> 18 #include <dm/uclass.h> 19 #include <fdt_support.h> 20 #include <time.h> 21 22 #ifdef CONFIG_ATSHA204A 23 # include <atsha204a-i2c.h> 24 #endif 25 26 #ifdef CONFIG_WDT_ORION 27 # include <wdt.h> 28 #endif 29 30 #include "../drivers/ddr/marvell/a38x/ddr3_init.h" 31 #include <../serdes/a38x/high_speed_env_spec.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 #define OMNIA_I2C_EEPROM_DM_NAME "i2c@0" 36 #define OMNIA_I2C_EEPROM 0x54 37 #define OMNIA_I2C_EEPROM_CONFIG_ADDR 0x0 38 #define OMNIA_I2C_EEPROM_ADDRLEN 2 39 #define OMNIA_I2C_EEPROM_MAGIC 0x0341a034 40 41 #define OMNIA_I2C_MCU_DM_NAME "i2c@0" 42 #define OMNIA_I2C_MCU_ADDR_STATUS 0x1 43 #define OMNIA_I2C_MCU_SATA 0x20 44 #define OMNIA_I2C_MCU_CARDDET 0x10 45 #define OMNIA_I2C_MCU 0x2a 46 #define OMNIA_I2C_MCU_WDT_ADDR 0x0b 47 48 #define OMNIA_ATSHA204_OTP_VERSION 0 49 #define OMNIA_ATSHA204_OTP_SERIAL 1 50 #define OMNIA_ATSHA204_OTP_MAC0 3 51 #define OMNIA_ATSHA204_OTP_MAC1 4 52 53 #define MVTWSI_ARMADA_DEBUG_REG 0x8c 54 55 /* 56 * Those values and defines are taken from the Marvell U-Boot version 57 * "u-boot-2013.01-2014_T3.0" 58 */ 59 #define OMNIA_GPP_OUT_ENA_LOW \ 60 (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \ 61 BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \ 62 BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31))) 63 #define OMNIA_GPP_OUT_ENA_MID \ 64 (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \ 65 BIT(16) | BIT(17) | BIT(18))) 66 67 #define OMNIA_GPP_OUT_VAL_LOW 0x0 68 #define OMNIA_GPP_OUT_VAL_MID 0x0 69 #define OMNIA_GPP_POL_LOW 0x0 70 #define OMNIA_GPP_POL_MID 0x0 71 72 static struct serdes_map board_serdes_map_pex[] = { 73 {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, 74 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 75 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, 76 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 77 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, 78 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0} 79 }; 80 81 static struct serdes_map board_serdes_map_sata[] = { 82 {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 83 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 84 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, 85 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 86 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, 87 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0} 88 }; 89 90 static bool omnia_detect_sata(void) 91 { 92 struct udevice *bus, *dev; 93 int ret, retry = 3; 94 u16 mode; 95 96 puts("SERDES0 card detect: "); 97 98 if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) { 99 puts("Cannot find MCU bus!\n"); 100 return false; 101 } 102 103 ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev); 104 if (ret) { 105 puts("Cannot get MCU chip!\n"); 106 return false; 107 } 108 109 for (; retry > 0; --retry) { 110 ret = dm_i2c_read(dev, OMNIA_I2C_MCU_ADDR_STATUS, (uchar *) &mode, 2); 111 if (!ret) 112 break; 113 } 114 115 if (!retry) { 116 puts("I2C read failed! Default PEX\n"); 117 return false; 118 } 119 120 if (!(mode & OMNIA_I2C_MCU_CARDDET)) { 121 puts("NONE\n"); 122 return false; 123 } 124 125 if (mode & OMNIA_I2C_MCU_SATA) { 126 puts("SATA\n"); 127 return true; 128 } else { 129 puts("PEX\n"); 130 return false; 131 } 132 } 133 134 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) 135 { 136 if (omnia_detect_sata()) { 137 *serdes_map_array = board_serdes_map_sata; 138 *count = ARRAY_SIZE(board_serdes_map_sata); 139 } else { 140 *serdes_map_array = board_serdes_map_pex; 141 *count = ARRAY_SIZE(board_serdes_map_pex); 142 } 143 144 return 0; 145 } 146 147 struct omnia_eeprom { 148 u32 magic; 149 u32 ramsize; 150 char region[4]; 151 u32 crc; 152 }; 153 154 static bool omnia_read_eeprom(struct omnia_eeprom *oep) 155 { 156 struct udevice *bus, *dev; 157 int ret, crc, retry = 3; 158 159 if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_EEPROM_DM_NAME, &bus)) { 160 puts("Cannot find EEPROM bus\n"); 161 return false; 162 } 163 164 ret = i2c_get_chip(bus, OMNIA_I2C_EEPROM, OMNIA_I2C_EEPROM_ADDRLEN, &dev); 165 if (ret) { 166 puts("Cannot get EEPROM chip\n"); 167 return false; 168 } 169 170 for (; retry > 0; --retry) { 171 ret = dm_i2c_read(dev, OMNIA_I2C_EEPROM_CONFIG_ADDR, (uchar *) oep, sizeof(struct omnia_eeprom)); 172 if (ret) 173 continue; 174 175 if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) { 176 puts("I2C EEPROM missing magic number!\n"); 177 continue; 178 } 179 180 crc = crc32(0, (unsigned char *) oep, 181 sizeof(struct omnia_eeprom) - 4); 182 if (crc == oep->crc) { 183 break; 184 } else { 185 printf("CRC of EEPROM memory config failed! " 186 "calc=0x%04x saved=0x%04x\n", crc, oep->crc); 187 } 188 } 189 190 if (!retry) { 191 puts("I2C EEPROM read failed!\n"); 192 return false; 193 } 194 195 return true; 196 } 197 198 /* 199 * Define the DDR layout / topology here in the board file. This will 200 * be used by the DDR3 init code in the SPL U-Boot version to configure 201 * the DDR3 controller. 202 */ 203 static struct mv_ddr_topology_map board_topology_map_1g = { 204 DEBUG_LEVEL_ERROR, 205 0x1, /* active interfaces */ 206 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ 207 { { { {0x1, 0, 0, 0}, 208 {0x1, 0, 0, 0}, 209 {0x1, 0, 0, 0}, 210 {0x1, 0, 0, 0}, 211 {0x1, 0, 0, 0} }, 212 SPEED_BIN_DDR_1600K, /* speed_bin */ 213 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */ 214 MV_DDR_DIE_CAP_4GBIT, /* mem_size */ 215 DDR_FREQ_800, /* frequency */ 216 0, 0, /* cas_wl cas_l */ 217 MV_DDR_TEMP_NORMAL} }, /* temperature */ 218 BUS_MASK_32BIT, /* Busses mask */ 219 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ 220 { {0} }, /* raw spd data */ 221 {0} /* timing parameters */ 222 }; 223 224 static struct mv_ddr_topology_map board_topology_map_2g = { 225 DEBUG_LEVEL_ERROR, 226 0x1, /* active interfaces */ 227 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ 228 { { { {0x1, 0, 0, 0}, 229 {0x1, 0, 0, 0}, 230 {0x1, 0, 0, 0}, 231 {0x1, 0, 0, 0}, 232 {0x1, 0, 0, 0} }, 233 SPEED_BIN_DDR_1600K, /* speed_bin */ 234 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */ 235 MV_DDR_DIE_CAP_8GBIT, /* mem_size */ 236 DDR_FREQ_800, /* frequency */ 237 0, 0, /* cas_wl cas_l */ 238 MV_DDR_TEMP_NORMAL} }, /* temperature */ 239 BUS_MASK_32BIT, /* Busses mask */ 240 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ 241 { {0} }, /* raw spd data */ 242 {0} /* timing parameters */ 243 }; 244 245 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) 246 { 247 static int mem = 0; 248 struct omnia_eeprom oep; 249 250 /* Get the board config from EEPROM */ 251 if (mem == 0) { 252 if(!omnia_read_eeprom(&oep)) 253 goto out; 254 255 printf("Memory config in EEPROM: 0x%02x\n", oep.ramsize); 256 257 if (oep.ramsize == 0x2) 258 mem = 2; 259 else 260 mem = 1; 261 } 262 263 out: 264 /* Hardcoded fallback */ 265 if (mem == 0) { 266 puts("WARNING: Memory config from EEPROM read failed.\n"); 267 puts("Falling back to default 1GiB map.\n"); 268 mem = 1; 269 } 270 271 /* Return the board topology as defined in the board code */ 272 if (mem == 1) 273 return &board_topology_map_1g; 274 if (mem == 2) 275 return &board_topology_map_2g; 276 277 return &board_topology_map_1g; 278 } 279 280 #ifndef CONFIG_SPL_BUILD 281 static int set_regdomain(void) 282 { 283 struct omnia_eeprom oep; 284 char rd[3] = {' ', ' ', 0}; 285 286 if (omnia_read_eeprom(&oep)) 287 memcpy(rd, &oep.region, 2); 288 else 289 puts("EEPROM regdomain read failed.\n"); 290 291 printf("Regdomain set to %s\n", rd); 292 return env_set("regdomain", rd); 293 } 294 #endif 295 296 int board_early_init_f(void) 297 { 298 u32 i2c_debug_reg; 299 300 /* Configure MPP */ 301 writel(0x11111111, MVEBU_MPP_BASE + 0x00); 302 writel(0x11111111, MVEBU_MPP_BASE + 0x04); 303 writel(0x11244011, MVEBU_MPP_BASE + 0x08); 304 writel(0x22222111, MVEBU_MPP_BASE + 0x0c); 305 writel(0x22200002, MVEBU_MPP_BASE + 0x10); 306 writel(0x30042022, MVEBU_MPP_BASE + 0x14); 307 writel(0x55550555, MVEBU_MPP_BASE + 0x18); 308 writel(0x00005550, MVEBU_MPP_BASE + 0x1c); 309 310 /* Set GPP Out value */ 311 writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); 312 writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); 313 314 /* Set GPP Polarity */ 315 writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); 316 writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); 317 318 /* Set GPP Out Enable */ 319 writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); 320 writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); 321 322 /* Disable I2C debug mode blocking 0x64 I2C address */ 323 i2c_debug_reg = readl(MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG); 324 i2c_debug_reg &= ~(1<<18); 325 writel(i2c_debug_reg, MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG); 326 327 return 0; 328 } 329 330 #ifndef CONFIG_SPL_BUILD 331 static bool disable_mcu_watchdog(void) 332 { 333 struct udevice *bus, *dev; 334 int ret, retry = 3; 335 uchar buf[1] = {0x0}; 336 337 if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) { 338 puts("Cannot find MCU bus! Can not disable MCU WDT.\n"); 339 return false; 340 } 341 342 ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev); 343 if (ret) { 344 puts("Cannot get MCU chip! Can not disable MCU WDT.\n"); 345 return false; 346 } 347 348 for (; retry > 0; --retry) 349 if (!dm_i2c_write(dev, OMNIA_I2C_MCU_WDT_ADDR, (uchar *) buf, 1)) 350 break; 351 352 if (retry <= 0) { 353 puts("I2C MCU watchdog failed to disable!\n"); 354 return false; 355 } 356 357 return true; 358 } 359 #endif 360 361 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION) 362 static struct udevice *watchdog_dev = NULL; 363 #endif 364 365 int board_init(void) 366 { 367 /* adress of boot parameters */ 368 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 369 370 #ifndef CONFIG_SPL_BUILD 371 # ifdef CONFIG_WDT_ORION 372 if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { 373 puts("Cannot find Armada 385 watchdog!\n"); 374 } else { 375 puts("Enabling Armada 385 watchdog.\n"); 376 wdt_start(watchdog_dev, (u32) 25000000 * 120, 0); 377 } 378 # endif 379 380 if (disable_mcu_watchdog()) 381 puts("Disabled MCU startup watchdog.\n"); 382 383 set_regdomain(); 384 #endif 385 386 return 0; 387 } 388 389 #ifdef CONFIG_WATCHDOG 390 /* Called by macro WATCHDOG_RESET */ 391 void watchdog_reset(void) 392 { 393 # if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION) 394 static ulong next_reset = 0; 395 ulong now; 396 397 if (!watchdog_dev) 398 return; 399 400 now = timer_get_us(); 401 402 /* Do not reset the watchdog too often */ 403 if (now > next_reset) { 404 wdt_reset(watchdog_dev); 405 next_reset = now + 1000; 406 } 407 # endif 408 } 409 #endif 410 411 int board_late_init(void) 412 { 413 #ifndef CONFIG_SPL_BUILD 414 set_regdomain(); 415 #endif 416 417 return 0; 418 } 419 420 #ifdef CONFIG_ATSHA204A 421 static struct udevice *get_atsha204a_dev(void) 422 { 423 static struct udevice *dev = NULL; 424 425 if (dev != NULL) 426 return dev; 427 428 if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) { 429 puts("Cannot find ATSHA204A on I2C bus!\n"); 430 dev = NULL; 431 } 432 433 return dev; 434 } 435 #endif 436 437 int checkboard(void) 438 { 439 u32 version_num, serial_num; 440 int err = 1; 441 442 #ifdef CONFIG_ATSHA204A 443 struct udevice *dev = get_atsha204a_dev(); 444 445 if (dev) { 446 err = atsha204a_wakeup(dev); 447 if (err) 448 goto out; 449 450 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, 451 OMNIA_ATSHA204_OTP_VERSION, 452 (u8 *) &version_num); 453 if (err) 454 goto out; 455 456 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, 457 OMNIA_ATSHA204_OTP_SERIAL, 458 (u8 *) &serial_num); 459 if (err) 460 goto out; 461 462 atsha204a_sleep(dev); 463 } 464 465 out: 466 #endif 467 468 if (err) 469 printf("Board: Turris Omnia (ver N/A). SN: N/A\n"); 470 else 471 printf("Board: Turris Omnia SNL %08X%08X\n", 472 be32_to_cpu(version_num), be32_to_cpu(serial_num)); 473 474 return 0; 475 } 476 477 static void increment_mac(u8 *mac) 478 { 479 int i; 480 481 for (i = 5; i >= 3; i--) { 482 mac[i] += 1; 483 if (mac[i]) 484 break; 485 } 486 } 487 488 int misc_init_r(void) 489 { 490 #ifdef CONFIG_ATSHA204A 491 int err; 492 struct udevice *dev = get_atsha204a_dev(); 493 u8 mac0[4], mac1[4], mac[6]; 494 495 if (!dev) 496 goto out; 497 498 err = atsha204a_wakeup(dev); 499 if (err) 500 goto out; 501 502 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, 503 OMNIA_ATSHA204_OTP_MAC0, mac0); 504 if (err) 505 goto out; 506 507 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, 508 OMNIA_ATSHA204_OTP_MAC1, mac1); 509 if (err) 510 goto out; 511 512 atsha204a_sleep(dev); 513 514 mac[0] = mac0[1]; 515 mac[1] = mac0[2]; 516 mac[2] = mac0[3]; 517 mac[3] = mac1[1]; 518 mac[4] = mac1[2]; 519 mac[5] = mac1[3]; 520 521 if (is_valid_ethaddr(mac)) 522 eth_env_set_enetaddr("ethaddr", mac); 523 524 increment_mac(mac); 525 526 if (is_valid_ethaddr(mac)) 527 eth_env_set_enetaddr("eth1addr", mac); 528 529 increment_mac(mac); 530 531 if (is_valid_ethaddr(mac)) 532 eth_env_set_enetaddr("eth2addr", mac); 533 534 out: 535 #endif 536 537 return 0; 538 } 539 540