1*18739e2cSSimon Glass /* 2*18739e2cSSimon Glass * From Coreboot file of same name 3*18739e2cSSimon Glass * 4*18739e2cSSimon Glass * Copyright (C) 2007-2009 coresystems GmbH 5*18739e2cSSimon Glass * 2012 secunet Security Networks AG 6*18739e2cSSimon Glass * 7*18739e2cSSimon Glass * SPDX-License-Identifier: GPL-2.0 8*18739e2cSSimon Glass */ 9*18739e2cSSimon Glass 10*18739e2cSSimon Glass #ifndef _ASM_SPEEDSTEP_H 11*18739e2cSSimon Glass #define _ASM_SPEEDSTEP_H 12*18739e2cSSimon Glass 13*18739e2cSSimon Glass /* Magic value used to locate speedstep configuration in the device tree */ 14*18739e2cSSimon Glass #define SPEEDSTEP_APIC_MAGIC 0xACAC 15*18739e2cSSimon Glass 16*18739e2cSSimon Glass /* MWAIT coordination I/O base address. This must match 17*18739e2cSSimon Glass * the \_PR_.CPU0 PM base address. 18*18739e2cSSimon Glass */ 19*18739e2cSSimon Glass #define PMB0_BASE 0x510 20*18739e2cSSimon Glass 21*18739e2cSSimon Glass /* PMB1: I/O port that triggers SMI once cores are in the same state. 22*18739e2cSSimon Glass * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] 23*18739e2cSSimon Glass */ 24*18739e2cSSimon Glass #define PMB1_BASE 0x800 25*18739e2cSSimon Glass 26*18739e2cSSimon Glass struct sst_state { 27*18739e2cSSimon Glass uint8_t dynfsb:1; /* whether this is SLFM */ 28*18739e2cSSimon Glass uint8_t nonint:1; /* add .5 to ratio */ 29*18739e2cSSimon Glass uint8_t ratio:6; 30*18739e2cSSimon Glass uint8_t vid; 31*18739e2cSSimon Glass uint8_t is_turbo; 32*18739e2cSSimon Glass uint8_t is_slfm; 33*18739e2cSSimon Glass uint32_t power; 34*18739e2cSSimon Glass }; 35*18739e2cSSimon Glass #define SPEEDSTEP_RATIO_SHIFT 8 36*18739e2cSSimon Glass #define SPEEDSTEP_RATIO_DYNFSB_SHIFT (7 + SPEEDSTEP_RATIO_SHIFT) 37*18739e2cSSimon Glass #define SPEEDSTEP_RATIO_DYNFSB (1 << SPEEDSTEP_RATIO_DYNFSB_SHIFT) 38*18739e2cSSimon Glass #define SPEEDSTEP_RATIO_NONINT_SHIFT (6 + SPEEDSTEP_RATIO_SHIFT) 39*18739e2cSSimon Glass #define SPEEDSTEP_RATIO_NONINT (1 << SPEEDSTEP_RATIO_NONINT_SHIFT) 40*18739e2cSSimon Glass #define SPEEDSTEP_RATIO_VALUE_MASK (0x1f << SPEEDSTEP_RATIO_SHIFT) 41*18739e2cSSimon Glass #define SPEEDSTEP_VID_MASK 0x3f 42*18739e2cSSimon Glass #define SPEEDSTEP_STATE_FROM_MSR(val, mask) ((struct sst_state){ \ 43*18739e2cSSimon Glass 0, /* dynfsb won't be read. */ \ 44*18739e2cSSimon Glass ((val & mask) & SPEEDSTEP_RATIO_NONINT) ? 1 : 0, \ 45*18739e2cSSimon Glass (((val & mask) & SPEEDSTEP_RATIO_VALUE_MASK) \ 46*18739e2cSSimon Glass >> SPEEDSTEP_RATIO_SHIFT), \ 47*18739e2cSSimon Glass (val & mask) & SPEEDSTEP_VID_MASK, \ 48*18739e2cSSimon Glass 0, /* not turbo by default */ \ 49*18739e2cSSimon Glass 0, /* not slfm by default */ \ 50*18739e2cSSimon Glass 0 /* power is hardcoded in software. */ \ 51*18739e2cSSimon Glass }) 52*18739e2cSSimon Glass #define SPEEDSTEP_ENCODE_STATE(state) ( \ 53*18739e2cSSimon Glass ((uint16_t)(state).dynfsb << SPEEDSTEP_RATIO_DYNFSB_SHIFT) | \ 54*18739e2cSSimon Glass ((uint16_t)(state).nonint << SPEEDSTEP_RATIO_NONINT_SHIFT) | \ 55*18739e2cSSimon Glass ((uint16_t)(state).ratio << SPEEDSTEP_RATIO_SHIFT) | \ 56*18739e2cSSimon Glass ((uint16_t)(state).vid & SPEEDSTEP_VID_MASK)) 57*18739e2cSSimon Glass #define SPEEDSTEP_DOUBLE_RATIO(state) ( \ 58*18739e2cSSimon Glass ((uint8_t)(state).ratio * 2) + (state).nonint) 59*18739e2cSSimon Glass 60*18739e2cSSimon Glass struct sst_params { 61*18739e2cSSimon Glass struct sst_state slfm; 62*18739e2cSSimon Glass struct sst_state min; 63*18739e2cSSimon Glass struct sst_state max; 64*18739e2cSSimon Glass struct sst_state turbo; 65*18739e2cSSimon Glass }; 66*18739e2cSSimon Glass 67*18739e2cSSimon Glass /* Looking at core2's spec, the highest normal bus ratio for an eist enabled 68*18739e2cSSimon Glass processor is 14, the lowest is always 6. This makes 5 states with the 69*18739e2cSSimon Glass minimal step width of 2. With turbo mode and super LFM we have at most 7. */ 70*18739e2cSSimon Glass #define SPEEDSTEP_MAX_NORMAL_STATES 5 71*18739e2cSSimon Glass #define SPEEDSTEP_MAX_STATES (SPEEDSTEP_MAX_NORMAL_STATES + 2) 72*18739e2cSSimon Glass struct sst_table { 73*18739e2cSSimon Glass /* Table of p-states for EMTTM and ACPI by decreasing performance. */ 74*18739e2cSSimon Glass struct sst_state states[SPEEDSTEP_MAX_STATES]; 75*18739e2cSSimon Glass int num_states; 76*18739e2cSSimon Glass }; 77*18739e2cSSimon Glass 78*18739e2cSSimon Glass void speedstep_gen_pstates(struct sst_table *); 79*18739e2cSSimon Glass 80*18739e2cSSimon Glass #define SPEEDSTEP_MAX_POWER_YONAH 31000 81*18739e2cSSimon Glass #define SPEEDSTEP_MIN_POWER_YONAH 13100 82*18739e2cSSimon Glass #define SPEEDSTEP_MAX_POWER_MEROM 35000 83*18739e2cSSimon Glass #define SPEEDSTEP_MIN_POWER_MEROM 25000 84*18739e2cSSimon Glass #define SPEEDSTEP_SLFM_POWER_MEROM 12000 85*18739e2cSSimon Glass #define SPEEDSTEP_MAX_POWER_PENRYN 35000 86*18739e2cSSimon Glass #define SPEEDSTEP_MIN_POWER_PENRYN 15000 87*18739e2cSSimon Glass #define SPEEDSTEP_SLFM_POWER_PENRYN 12000 88*18739e2cSSimon Glass 89*18739e2cSSimon Glass #endif 90