1*83d290c5STom Rini /* SPDX-License-Identifier: Intel */ 21021af4dSSimon Glass /* 31021af4dSSimon Glass * Copyright (C) 2013, Intel Corporation 41021af4dSSimon Glass * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 51021af4dSSimon Glass */ 61021af4dSSimon Glass 71021af4dSSimon Glass #ifndef _FSP_HEADER_H_ 81021af4dSSimon Glass #define _FSP_HEADER_H_ 91021af4dSSimon Glass 101021af4dSSimon Glass #define FSP_HEADER_OFF 0x94 /* Fixed FSP header offset in the FSP image */ 111021af4dSSimon Glass 121021af4dSSimon Glass struct __packed fsp_header { 131021af4dSSimon Glass u32 sign; /* 'FSPH' */ 141021af4dSSimon Glass u32 hdr_len; /* header length */ 151021af4dSSimon Glass u8 reserved1[3]; 161021af4dSSimon Glass u8 hdr_rev; /* header rev */ 171021af4dSSimon Glass u32 img_rev; /* image rev */ 181021af4dSSimon Glass char img_id[8]; /* signature string */ 191021af4dSSimon Glass u32 img_size; /* image size */ 201021af4dSSimon Glass u32 img_base; /* image base */ 211021af4dSSimon Glass u32 img_attr; /* image attribute */ 221021af4dSSimon Glass u32 cfg_region_off; /* configuration region offset */ 231021af4dSSimon Glass u32 cfg_region_size; /* configuration region size */ 241021af4dSSimon Glass u32 api_num; /* number of API entries */ 251021af4dSSimon Glass u32 fsp_tempram_init; /* tempram_init offset */ 261021af4dSSimon Glass u32 fsp_init; /* fsp_init offset */ 271021af4dSSimon Glass u32 fsp_notify; /* fsp_notify offset */ 28b3fd2126SBin Meng u32 fsp_mem_init; /* fsp_mem_init offset */ 29b3fd2126SBin Meng u32 fsp_tempram_exit; /* fsp_tempram_exit offset */ 30b3fd2126SBin Meng u32 fsp_silicon_init; /* fsp_silicon_init offset */ 311021af4dSSimon Glass }; 321021af4dSSimon Glass 33b3fd2126SBin Meng #define FSP_HEADER_REVISION_1 1 34b3fd2126SBin Meng #define FSP_HEADER_REVISION_2 2 35b3fd2126SBin Meng 36b3fd2126SBin Meng #define FSP_ATTR_GRAPHICS_SUPPORT (1 << 0) 37b3fd2126SBin Meng 381021af4dSSimon Glass #endif 39