1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 248cf8b83SBin Meng /* 348cf8b83SBin Meng * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> 448cf8b83SBin Meng */ 548cf8b83SBin Meng 648cf8b83SBin Meng #ifndef _QUARK_IOMAP_H_ 748cf8b83SBin Meng #define _QUARK_IOMAP_H_ 848cf8b83SBin Meng 948cf8b83SBin Meng /* Memory Mapped IO bases */ 1048cf8b83SBin Meng 1148cf8b83SBin Meng /* ESRAM */ 1248cf8b83SBin Meng #define ESRAM_BASE_ADDRESS CONFIG_ESRAM_BASE 1348cf8b83SBin Meng #define ESRAM_BASE_SIZE ESRAM_SIZE 1448cf8b83SBin Meng 1548cf8b83SBin Meng /* PCI Configuration Space */ 1648cf8b83SBin Meng #define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE 1748cf8b83SBin Meng #define MCFG_BASE_SIZE 0x10000000 1848cf8b83SBin Meng 1948cf8b83SBin Meng /* High Performance Event Timer */ 2048cf8b83SBin Meng #define HPET_BASE_ADDRESS 0xfed00000 2148cf8b83SBin Meng #define HPET_BASE_SIZE 0x400 2248cf8b83SBin Meng 2348cf8b83SBin Meng /* Root Complex Base Address */ 2448cf8b83SBin Meng #define RCBA_BASE_ADDRESS CONFIG_RCBA_BASE 2548cf8b83SBin Meng #define RCBA_BASE_SIZE 0x4000 2648cf8b83SBin Meng 2748cf8b83SBin Meng /* IO Port bases */ 2848cf8b83SBin Meng #define ACPI_PM1_BASE_ADDRESS CONFIG_ACPI_PM1_BASE 2948cf8b83SBin Meng #define ACPI_PM1_BASE_SIZE 0x10 3048cf8b83SBin Meng 3148cf8b83SBin Meng #define ACPI_PBLK_BASE_ADDRESS CONFIG_ACPI_PBLK_BASE 3248cf8b83SBin Meng #define ACPI_PBLK_BASE_SIZE 0x10 3348cf8b83SBin Meng 3448cf8b83SBin Meng #define SPI_DMA_BASE_ADDRESS CONFIG_SPI_DMA_BASE 3548cf8b83SBin Meng #define SPI_DMA_BASE_SIZE 0x10 3648cf8b83SBin Meng 3748cf8b83SBin Meng #define GPIO_BASE_ADDRESS CONFIG_GPIO_BASE 3848cf8b83SBin Meng #define GPIO_BASE_SIZE 0x80 3948cf8b83SBin Meng 4048cf8b83SBin Meng #define ACPI_GPE0_BASE_ADDRESS CONFIG_ACPI_GPE0_BASE 4148cf8b83SBin Meng #define ACPI_GPE0_BASE_SIZE 0x40 4248cf8b83SBin Meng 4348cf8b83SBin Meng #define WDT_BASE_ADDRESS CONFIG_WDT_BASE 4448cf8b83SBin Meng #define WDT_BASE_SIZE 0x40 4548cf8b83SBin Meng 4648cf8b83SBin Meng #endif /* _QUARK_IOMAP_H_ */ 47