1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 2f5fbbe95SSimon Glass /* 3f5fbbe95SSimon Glass * From Coreboot file of the same name 4f5fbbe95SSimon Glass * 5f5fbbe95SSimon Glass * Copyright (C) 2011 The ChromiumOS Authors. 6f5fbbe95SSimon Glass */ 7f5fbbe95SSimon Glass 8f5fbbe95SSimon Glass #ifndef _ASM_ARCH_MODEL_206AX_H 9f5fbbe95SSimon Glass #define _ASM_ARCH_MODEL_206AX_H 10f5fbbe95SSimon Glass 11f5fbbe95SSimon Glass /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ 12f5fbbe95SSimon Glass #define SANDYBRIDGE_BCLK 100 13f5fbbe95SSimon Glass 14f5fbbe95SSimon Glass #define CPUID_VMX (1 << 5) 15f5fbbe95SSimon Glass #define CPUID_SMX (1 << 6) 16f5fbbe95SSimon Glass #define MSR_FEATURE_CONFIG 0x13c 17f5fbbe95SSimon Glass #define IA32_PLATFORM_DCA_CAP 0x1f8 18f5fbbe95SSimon Glass #define IA32_MISC_ENABLE 0x1a0 19f5fbbe95SSimon Glass #define MSR_TEMPERATURE_TARGET 0x1a2 20f5fbbe95SSimon Glass #define IA32_THERM_INTERRUPT 0x19b 21f5fbbe95SSimon Glass #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 22f5fbbe95SSimon Glass #define ENERGY_POLICY_PERFORMANCE 0 23f5fbbe95SSimon Glass #define ENERGY_POLICY_NORMAL 6 24f5fbbe95SSimon Glass #define ENERGY_POLICY_POWERSAVE 15 25f5fbbe95SSimon Glass #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 26f5fbbe95SSimon Glass #define MSR_LT_LOCK_MEMORY 0x2e7 27f5fbbe95SSimon Glass #define IA32_MC0_STATUS 0x401 28f5fbbe95SSimon Glass 29f5fbbe95SSimon Glass #define MSR_MISC_PWR_MGMT 0x1aa 30f5fbbe95SSimon Glass #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) 31f5fbbe95SSimon Glass 32f5fbbe95SSimon Glass #define MSR_PKGC3_IRTL 0x60a 33f5fbbe95SSimon Glass #define MSR_PKGC6_IRTL 0x60b 34f5fbbe95SSimon Glass #define MSR_PKGC7_IRTL 0x60c 35f5fbbe95SSimon Glass #define IRTL_VALID (1 << 15) 36f5fbbe95SSimon Glass #define IRTL_1_NS (0 << 10) 37f5fbbe95SSimon Glass #define IRTL_32_NS (1 << 10) 38f5fbbe95SSimon Glass #define IRTL_1024_NS (2 << 10) 39f5fbbe95SSimon Glass #define IRTL_32768_NS (3 << 10) 40f5fbbe95SSimon Glass #define IRTL_1048576_NS (4 << 10) 41f5fbbe95SSimon Glass #define IRTL_33554432_NS (5 << 10) 42f5fbbe95SSimon Glass #define IRTL_RESPONSE_MASK (0x3ff) 43f5fbbe95SSimon Glass 44f5fbbe95SSimon Glass #define MSR_PP0_CURRENT_CONFIG 0x601 45f5fbbe95SSimon Glass #define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */ 46f5fbbe95SSimon Glass #define MSR_PP1_CURRENT_CONFIG 0x602 47f5fbbe95SSimon Glass #define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */ 48f5fbbe95SSimon Glass #define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */ 49f5fbbe95SSimon Glass #define MSR_PKG_POWER_SKU 0x614 50f5fbbe95SSimon Glass 51f5fbbe95SSimon Glass #define IVB_CONFIG_TDP_MIN_CPUID 0x306a2 52f5fbbe95SSimon Glass #define MSR_CONFIG_TDP_LEVEL1 0x649 53f5fbbe95SSimon Glass #define MSR_CONFIG_TDP_LEVEL2 0x64a 54f5fbbe95SSimon Glass #define MSR_CONFIG_TDP_CONTROL 0x64b 55f5fbbe95SSimon Glass 56f5fbbe95SSimon Glass /* P-state configuration */ 57f5fbbe95SSimon Glass #define PSS_MAX_ENTRIES 8 58f5fbbe95SSimon Glass #define PSS_RATIO_STEP 2 59f5fbbe95SSimon Glass #define PSS_LATENCY_TRANSITION 10 60f5fbbe95SSimon Glass #define PSS_LATENCY_BUSMASTER 10 61f5fbbe95SSimon Glass 6224774278SSimon Glass /* Configure power limits for turbo mode */ 6324774278SSimon Glass void set_power_limits(u8 power_limit_1_time); 6424774278SSimon Glass int cpu_config_tdp_levels(void); 6524774278SSimon Glass 66f5fbbe95SSimon Glass #endif 67