1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 2b24f5c4fSSimon Glass /* 3b24f5c4fSSimon Glass * Copyright (c) 2016 Google, Inc 4b24f5c4fSSimon Glass * 5b24f5c4fSSimon Glass * From Coreboot src/soc/intel/broadwell/include/soc/gpio.h 6b24f5c4fSSimon Glass */ 7b24f5c4fSSimon Glass 8b24f5c4fSSimon Glass #ifndef __ASM_ARCH_GPIO 9b24f5c4fSSimon Glass #define __ASM_ARCH_GPIO 10b24f5c4fSSimon Glass 11b24f5c4fSSimon Glass #define GPIO_PER_BANK 32 12b24f5c4fSSimon Glass #define GPIO_BANKS 3 13b24f5c4fSSimon Glass 14b24f5c4fSSimon Glass struct broadwell_bank_platdata { 15b24f5c4fSSimon Glass uint16_t base_addr; 16b24f5c4fSSimon Glass const char *bank_name; 17b24f5c4fSSimon Glass int bank; 18b24f5c4fSSimon Glass }; 19b24f5c4fSSimon Glass 20b24f5c4fSSimon Glass /* PCH-LP GPIOBASE Registers */ 21b24f5c4fSSimon Glass struct pch_lp_gpio_regs { 22b24f5c4fSSimon Glass u32 own[GPIO_BANKS]; 23b24f5c4fSSimon Glass u32 reserved0; 24b24f5c4fSSimon Glass 25b24f5c4fSSimon Glass u16 pirq_to_ioxapic; 26b24f5c4fSSimon Glass u16 reserved1[3]; 27b24f5c4fSSimon Glass u32 blink; 28b24f5c4fSSimon Glass u32 ser_blink; 29b24f5c4fSSimon Glass 30b24f5c4fSSimon Glass u32 ser_blink_cmdsts; 31b24f5c4fSSimon Glass u32 ser_blink_data; 32b24f5c4fSSimon Glass u16 gpi_nmi_en; 33b24f5c4fSSimon Glass u16 gpi_nmi_sts; 34b24f5c4fSSimon Glass u32 reserved2; 35b24f5c4fSSimon Glass 36b24f5c4fSSimon Glass u32 gpi_route[GPIO_BANKS]; 37b24f5c4fSSimon Glass u32 reserved3; 38b24f5c4fSSimon Glass 39b24f5c4fSSimon Glass u32 reserved4[4]; 40b24f5c4fSSimon Glass 41b24f5c4fSSimon Glass u32 alt_gpi_smi_sts; 42b24f5c4fSSimon Glass u32 alt_gpi_smi_en; 43b24f5c4fSSimon Glass u32 reserved5[2]; 44b24f5c4fSSimon Glass 45b24f5c4fSSimon Glass u32 rst_sel[GPIO_BANKS]; 46b24f5c4fSSimon Glass u32 reserved6; 47b24f5c4fSSimon Glass 48b24f5c4fSSimon Glass u32 reserved9[3]; 49b24f5c4fSSimon Glass u32 gpio_gc; 50b24f5c4fSSimon Glass 51b24f5c4fSSimon Glass u32 gpi_is[GPIO_BANKS]; 52b24f5c4fSSimon Glass u32 reserved10; 53b24f5c4fSSimon Glass 54b24f5c4fSSimon Glass u32 gpi_ie[GPIO_BANKS]; 55b24f5c4fSSimon Glass u32 reserved11; 56b24f5c4fSSimon Glass 57b24f5c4fSSimon Glass u32 reserved12[24]; 58b24f5c4fSSimon Glass 59b24f5c4fSSimon Glass struct { 60b24f5c4fSSimon Glass u32 conf_a; 61b24f5c4fSSimon Glass u32 conf_b; 62b24f5c4fSSimon Glass } config[GPIO_BANKS * GPIO_PER_BANK]; 63b24f5c4fSSimon Glass }; 64b24f5c4fSSimon Glass check_member(pch_lp_gpio_regs, gpi_ie[0], 0x90); 65b24f5c4fSSimon Glass check_member(pch_lp_gpio_regs, config[0], 0x100); 66b24f5c4fSSimon Glass 67b24f5c4fSSimon Glass enum { 68b24f5c4fSSimon Glass CONFA_MODE_SHIFT = 0, 69b24f5c4fSSimon Glass CONFA_MODE_GPIO = 1 << CONFA_MODE_SHIFT, 70b24f5c4fSSimon Glass 71b24f5c4fSSimon Glass CONFA_DIR_SHIFT = 2, 72b24f5c4fSSimon Glass CONFA_DIR_INPUT = 1 << CONFA_DIR_SHIFT, 73b24f5c4fSSimon Glass 74b24f5c4fSSimon Glass CONFA_INVERT_SHIFT = 3, 75b24f5c4fSSimon Glass CONFA_INVERT = 1 << CONFA_INVERT_SHIFT, 76b24f5c4fSSimon Glass 77b24f5c4fSSimon Glass CONFA_TRIGGER_SHIFT = 4, 78b24f5c4fSSimon Glass CONFA_TRIGGER_LEVEL = 1 << CONFA_TRIGGER_SHIFT, 79b24f5c4fSSimon Glass 80b24f5c4fSSimon Glass CONFA_LEVEL_SHIFT = 30, 81b24f5c4fSSimon Glass CONFA_LEVEL_HIGH = 1UL << CONFA_LEVEL_SHIFT, 82b24f5c4fSSimon Glass 83b24f5c4fSSimon Glass CONFA_OUTPUT_SHIFT = 31, 84b24f5c4fSSimon Glass CONFA_OUTPUT_HIGH = 1UL << CONFA_OUTPUT_SHIFT, 85b24f5c4fSSimon Glass 86b24f5c4fSSimon Glass CONFB_SENSE_SHIFT = 2, 87b24f5c4fSSimon Glass CONFB_SENSE_DISABLE = 1 << CONFB_SENSE_SHIFT, 88b24f5c4fSSimon Glass }; 89b24f5c4fSSimon Glass 90b24f5c4fSSimon Glass #endif 91