1*2f3f477bSSimon Glass /* 2*2f3f477bSSimon Glass * Copyright (c) 2016 Google, Inc 3*2f3f477bSSimon Glass * 4*2f3f477bSSimon Glass * SPDX-License-Identifier: GPL-2.0 5*2f3f477bSSimon Glass */ 6*2f3f477bSSimon Glass 7*2f3f477bSSimon Glass #ifndef __asm_arch_cpu_h 8*2f3f477bSSimon Glass #define __asm_arch_cpu_h 9*2f3f477bSSimon Glass 10*2f3f477bSSimon Glass /* CPU types */ 11*2f3f477bSSimon Glass #define HASWELL_FAMILY_ULT 0x40650 12*2f3f477bSSimon Glass #define BROADWELL_FAMILY_ULT 0x306d0 13*2f3f477bSSimon Glass 14*2f3f477bSSimon Glass /* Supported CPUIDs */ 15*2f3f477bSSimon Glass #define CPUID_HASWELL_A0 0x306c1 16*2f3f477bSSimon Glass #define CPUID_HASWELL_B0 0x306c2 17*2f3f477bSSimon Glass #define CPUID_HASWELL_C0 0x306c3 18*2f3f477bSSimon Glass #define CPUID_HASWELL_ULT_B0 0x40650 19*2f3f477bSSimon Glass #define CPUID_HASWELL_ULT 0x40651 20*2f3f477bSSimon Glass #define CPUID_HASWELL_HALO 0x40661 21*2f3f477bSSimon Glass #define CPUID_BROADWELL_C0 0x306d2 22*2f3f477bSSimon Glass #define CPUID_BROADWELL_D0 0x306d3 23*2f3f477bSSimon Glass #define CPUID_BROADWELL_E0 0x306d4 24*2f3f477bSSimon Glass 25*2f3f477bSSimon Glass /* Broadwell bus clock is fixed at 100MHz */ 26*2f3f477bSSimon Glass #define BROADWELL_BCLK 100 27*2f3f477bSSimon Glass 28*2f3f477bSSimon Glass #define BROADWELL_FAMILY_ULT 0x306d0 29*2f3f477bSSimon Glass 30*2f3f477bSSimon Glass #define CORE_THREAD_COUNT_MSR 0x35 31*2f3f477bSSimon Glass 32*2f3f477bSSimon Glass #define MSR_VR_CURRENT_CONFIG 0x601 33*2f3f477bSSimon Glass #define MSR_VR_MISC_CONFIG 0x603 34*2f3f477bSSimon Glass #define MSR_PKG_POWER_SKU 0x614 35*2f3f477bSSimon Glass #define MSR_DDR_RAPL_LIMIT 0x618 36*2f3f477bSSimon Glass #define MSR_VR_MISC_CONFIG2 0x636 37*2f3f477bSSimon Glass 38*2f3f477bSSimon Glass /* Latency times in units of 1024ns. */ 39*2f3f477bSSimon Glass #define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 40*2f3f477bSSimon Glass #define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 41*2f3f477bSSimon Glass #define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 42*2f3f477bSSimon Glass #define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 43*2f3f477bSSimon Glass #define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 44*2f3f477bSSimon Glass #define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef 45*2f3f477bSSimon Glass 46*2f3f477bSSimon Glass void cpu_set_power_limits(int power_limit_1_time); 47*2f3f477bSSimon Glass 48*2f3f477bSSimon Glass #endif 49