1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 22f3f477bSSimon Glass /* 32f3f477bSSimon Glass * Copyright (c) 2016 Google, Inc 42f3f477bSSimon Glass */ 52f3f477bSSimon Glass 62f3f477bSSimon Glass #ifndef __asm_arch_cpu_h 72f3f477bSSimon Glass #define __asm_arch_cpu_h 82f3f477bSSimon Glass 92f3f477bSSimon Glass /* CPU types */ 102f3f477bSSimon Glass #define HASWELL_FAMILY_ULT 0x40650 112f3f477bSSimon Glass #define BROADWELL_FAMILY_ULT 0x306d0 122f3f477bSSimon Glass 132f3f477bSSimon Glass /* Supported CPUIDs */ 142f3f477bSSimon Glass #define CPUID_HASWELL_A0 0x306c1 152f3f477bSSimon Glass #define CPUID_HASWELL_B0 0x306c2 162f3f477bSSimon Glass #define CPUID_HASWELL_C0 0x306c3 172f3f477bSSimon Glass #define CPUID_HASWELL_ULT_B0 0x40650 182f3f477bSSimon Glass #define CPUID_HASWELL_ULT 0x40651 192f3f477bSSimon Glass #define CPUID_HASWELL_HALO 0x40661 202f3f477bSSimon Glass #define CPUID_BROADWELL_C0 0x306d2 212f3f477bSSimon Glass #define CPUID_BROADWELL_D0 0x306d3 222f3f477bSSimon Glass #define CPUID_BROADWELL_E0 0x306d4 232f3f477bSSimon Glass 242f3f477bSSimon Glass /* Broadwell bus clock is fixed at 100MHz */ 252f3f477bSSimon Glass #define BROADWELL_BCLK 100 262f3f477bSSimon Glass 272f3f477bSSimon Glass #define BROADWELL_FAMILY_ULT 0x306d0 282f3f477bSSimon Glass 292f3f477bSSimon Glass #define CORE_THREAD_COUNT_MSR 0x35 302f3f477bSSimon Glass 312f3f477bSSimon Glass #define MSR_VR_CURRENT_CONFIG 0x601 322f3f477bSSimon Glass #define MSR_VR_MISC_CONFIG 0x603 332f3f477bSSimon Glass #define MSR_PKG_POWER_SKU 0x614 342f3f477bSSimon Glass #define MSR_DDR_RAPL_LIMIT 0x618 352f3f477bSSimon Glass #define MSR_VR_MISC_CONFIG2 0x636 362f3f477bSSimon Glass 372f3f477bSSimon Glass /* Latency times in units of 1024ns. */ 382f3f477bSSimon Glass #define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 392f3f477bSSimon Glass #define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 402f3f477bSSimon Glass #define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 412f3f477bSSimon Glass #define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 422f3f477bSSimon Glass #define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 432f3f477bSSimon Glass #define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef 442f3f477bSSimon Glass 452f3f477bSSimon Glass void cpu_set_power_limits(int power_limit_1_time); 462f3f477bSSimon Glass 472f3f477bSSimon Glass #endif 48