1*83d290c5STom Rini /* SPDX-License-Identifier: Intel */ 2fffad926SBin Meng /* 3fffad926SBin Meng * Copyright (C) 2015, Intel Corporation 4fffad926SBin Meng * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> 5fffad926SBin Meng */ 6fffad926SBin Meng 7fffad926SBin Meng #ifndef __FSP_VPD_H__ 8fffad926SBin Meng #define __FSP_VPD_H__ 9fffad926SBin Meng 10fffad926SBin Meng struct __packed memory_upd { 11fffad926SBin Meng u64 signature; /* Offset 0x0020 */ 12fffad926SBin Meng u8 revision; /* Offset 0x0028 */ 13fffad926SBin Meng u8 unused2[7]; /* Offset 0x0029 */ 14fffad926SBin Meng u16 mrc_init_tseg_size; /* Offset 0x0030 */ 15fffad926SBin Meng u16 mrc_init_mmio_size; /* Offset 0x0032 */ 16fffad926SBin Meng u8 mrc_init_spd_addr1; /* Offset 0x0034 */ 17fffad926SBin Meng u8 mrc_init_spd_addr2; /* Offset 0x0035 */ 18fffad926SBin Meng u8 mem_ch0_config; /* Offset 0x0036 */ 19fffad926SBin Meng u8 mem_ch1_config; /* Offset 0x0037 */ 20fffad926SBin Meng u32 memory_spd_ptr; /* Offset 0x0038 */ 21fffad926SBin Meng u8 igd_dvmt50_pre_alloc; /* Offset 0x003c */ 22fffad926SBin Meng u8 aperture_size; /* Offset 0x003d */ 23fffad926SBin Meng u8 gtt_size; /* Offset 0x003e */ 24fffad926SBin Meng u8 legacy_seg_decode; /* Offset 0x003f */ 25fffad926SBin Meng u8 enable_dvfs; /* Offset 0x0040 */ 26fffad926SBin Meng u8 memory_type; /* Offset 0x0041 */ 27fffad926SBin Meng u8 enable_ca_mirror; /* Offset 0x0042 */ 28fffad926SBin Meng u8 reserved[189]; /* Offset 0x0043 */ 29fffad926SBin Meng }; 30fffad926SBin Meng 31fffad926SBin Meng struct gpio_family { 32fffad926SBin Meng u32 confg; 33fffad926SBin Meng u32 confg_changes; 34fffad926SBin Meng u32 misc; 35fffad926SBin Meng u32 mmio_addr; 36fffad926SBin Meng wchar_t *name; 37fffad926SBin Meng }; 38fffad926SBin Meng 39fffad926SBin Meng struct gpio_pad { 40fffad926SBin Meng u32 confg0; 41fffad926SBin Meng u32 confg0_changes; 42fffad926SBin Meng u32 confg1; 43fffad926SBin Meng u32 confg1_changes; 44fffad926SBin Meng u32 community; 45fffad926SBin Meng u32 mmio_addr; 46fffad926SBin Meng wchar_t *name; 47fffad926SBin Meng u32 misc; 48fffad926SBin Meng }; 49fffad926SBin Meng 50fffad926SBin Meng struct __packed silicon_upd { 51fffad926SBin Meng u64 signature; /* Offset 0x0100 */ 52fffad926SBin Meng u8 revision; /* Offset 0x0108 */ 53fffad926SBin Meng u8 unused3[7]; /* Offset 0x0109 */ 54fffad926SBin Meng u8 sdcard_mode; /* Offset 0x0110 */ 55fffad926SBin Meng u8 enable_hsuart0; /* Offset 0x0111 */ 56fffad926SBin Meng u8 enable_hsuart1; /* Offset 0x0112 */ 57fffad926SBin Meng u8 enable_azalia; /* Offset 0x0113 */ 58fffad926SBin Meng struct azalia_config *azalia_cfg_ptr; /* Offset 0x0114 */ 59fffad926SBin Meng u8 enable_sata; /* Offset 0x0118 */ 60fffad926SBin Meng u8 enable_xhci; /* Offset 0x0119 */ 61fffad926SBin Meng u8 lpe_mode; /* Offset 0x011a */ 62fffad926SBin Meng u8 enable_dma0; /* Offset 0x011b */ 63fffad926SBin Meng u8 enable_dma1; /* Offset 0x011c */ 64fffad926SBin Meng u8 enable_i2c0; /* Offset 0x011d */ 65fffad926SBin Meng u8 enable_i2c1; /* Offset 0x011e */ 66fffad926SBin Meng u8 enable_i2c2; /* Offset 0x011f */ 67fffad926SBin Meng u8 enable_i2c3; /* Offset 0x0120 */ 68fffad926SBin Meng u8 enable_i2c4; /* Offset 0x0121 */ 69fffad926SBin Meng u8 enable_i2c5; /* Offset 0x0122 */ 70fffad926SBin Meng u8 enable_i2c6; /* Offset 0x0123 */ 71fffad926SBin Meng u32 graphics_config_ptr; /* Offset 0x0124 */ 72fffad926SBin Meng struct gpio_family *gpio_familiy_ptr; /* Offset 0x0128 */ 73fffad926SBin Meng struct gpio_pad *gpio_pad_ptr; /* Offset 0x012c */ 74fffad926SBin Meng u8 disable_punit_pwr_config; /* Offset 0x0130 */ 75fffad926SBin Meng u8 chv_svid_config; /* Offset 0x0131 */ 76fffad926SBin Meng u8 disable_dptf; /* Offset 0x0132 */ 77fffad926SBin Meng u8 emmc_mode; /* Offset 0x0133 */ 78fffad926SBin Meng u8 usb3_clk_ssc; /* Offset 0x0134 */ 79fffad926SBin Meng u8 disp_clk_ssc; /* Offset 0x0135 */ 80fffad926SBin Meng u8 sata_clk_ssc; /* Offset 0x0136 */ 81fffad926SBin Meng u8 usb2_port0_pe_txi_set; /* Offset 0x0137 */ 82fffad926SBin Meng u8 usb2_port0_txi_set; /* Offset 0x0138 */ 83fffad926SBin Meng u8 usb2_port0_tx_emphasis_en; /* Offset 0x0139 */ 84fffad926SBin Meng u8 usb2_port0_tx_pe_half; /* Offset 0x013a */ 85fffad926SBin Meng u8 usb2_port1_pe_txi_set; /* Offset 0x013b */ 86fffad926SBin Meng u8 usb2_port1_txi_set; /* Offset 0x013c */ 87fffad926SBin Meng u8 usb2_port1_tx_emphasis_en; /* Offset 0x013d */ 88fffad926SBin Meng u8 usb2_port1_tx_pe_half; /* Offset 0x013e */ 89fffad926SBin Meng u8 usb2_port2_pe_txi_set; /* Offset 0x013f */ 90fffad926SBin Meng u8 usb2_port2_txi_set; /* Offset 0x0140 */ 91fffad926SBin Meng u8 usb2_port2_tx_emphasis_en; /* Offset 0x0141 */ 92fffad926SBin Meng u8 usb2_port2_tx_pe_half; /* Offset 0x0142 */ 93fffad926SBin Meng u8 usb2_port3_pe_txi_set; /* Offset 0x0143 */ 94fffad926SBin Meng u8 usb2_port3_txi_set; /* Offset 0x0144 */ 95fffad926SBin Meng u8 usb2_port3_tx_emphasis_en; /* Offset 0x0145 */ 96fffad926SBin Meng u8 usb2_port3_tx_pe_half; /* Offset 0x0146 */ 97fffad926SBin Meng u8 usb2_port4_pe_txi_set; /* Offset 0x0147 */ 98fffad926SBin Meng u8 usb2_port4_txi_set; /* Offset 0x0148 */ 99fffad926SBin Meng u8 usb2_port4_tx_emphasis_en; /* Offset 0x0149 */ 100fffad926SBin Meng u8 usb2_port4_tx_pe_half; /* Offset 0x014a */ 101fffad926SBin Meng u8 usb3_lane0_ow2tap_gen2_deemph3p5; /* Offset 0x014b */ 102fffad926SBin Meng u8 usb3_lane1_ow2tap_gen2_deemph3p5; /* Offset 0x014c */ 103fffad926SBin Meng u8 usb3_lane2_ow2tap_gen2_deemph3p5; /* Offset 0x014d */ 104fffad926SBin Meng u8 usb3_lane3_ow2tap_gen2_deemph3p5; /* Offset 0x014e */ 105fffad926SBin Meng u8 sata_speed; /* Offset 0x014f */ 106fffad926SBin Meng u8 usb_ssic_port; /* Offset 0x0150 */ 107fffad926SBin Meng u8 usb_hsic_port; /* Offset 0x0151 */ 108fffad926SBin Meng u8 pcie_rootport_speed; /* Offset 0x0152 */ 109fffad926SBin Meng u8 enable_ssic; /* Offset 0x0153 */ 110fffad926SBin Meng u32 logo_ptr; /* Offset 0x0154 */ 111fffad926SBin Meng u32 logo_size; /* Offset 0x0158 */ 112fffad926SBin Meng u8 rtc_lock; /* Offset 0x015c */ 113fffad926SBin Meng u8 pmic_i2c_bus; /* Offset 0x015d */ 114fffad926SBin Meng u8 enable_isp; /* Offset 0x015e */ 115fffad926SBin Meng u8 isp_pci_dev_config; /* Offset 0x015f */ 116fffad926SBin Meng u8 turbo_mode; /* Offset 0x0160 */ 117fffad926SBin Meng u8 pnp_settings; /* Offset 0x0161 */ 118fffad926SBin Meng u8 sd_detect_chk; /* Offset 0x0162 */ 119fffad926SBin Meng u8 reserved[411]; /* Offset 0x0163 */ 120fffad926SBin Meng }; 121fffad926SBin Meng 122fffad926SBin Meng #define MEMORY_UPD_ID 0x244450554d454d24 /* '$MEMUPD$' */ 123fffad926SBin Meng #define SILICON_UPD_ID 0x244450555f495324 /* '$SI_UPD$' */ 124fffad926SBin Meng 125fffad926SBin Meng struct __packed upd_region { 126fffad926SBin Meng u64 signature; /* Offset 0x0000 */ 127fffad926SBin Meng u8 revision; /* Offset 0x0008 */ 128fffad926SBin Meng u8 unused0[7]; /* Offset 0x0009 */ 129fffad926SBin Meng u32 memory_upd_offset; /* Offset 0x0010 */ 130fffad926SBin Meng u32 silicon_upd_offset; /* Offset 0x0014 */ 131fffad926SBin Meng u64 unused1; /* Offset 0x0018 */ 132fffad926SBin Meng struct memory_upd memory_upd; /* Offset 0x0020 */ 133fffad926SBin Meng struct silicon_upd silicon_upd; /* Offset 0x0100 */ 134fffad926SBin Meng u16 terminator; /* Offset 0x02fe */ 135fffad926SBin Meng }; 136fffad926SBin Meng 137fffad926SBin Meng #define VPD_IMAGE_ID 0x2450534657534224 /* '$BSWFSP$' */ 138fffad926SBin Meng 139fffad926SBin Meng struct __packed vpd_region { 140fffad926SBin Meng u64 sign; /* Offset 0x0000 */ 141fffad926SBin Meng u32 img_rev; /* Offset 0x0008 */ 142fffad926SBin Meng u32 upd_offset; /* Offset 0x000c */ 143fffad926SBin Meng }; 144fffad926SBin Meng 145fffad926SBin Meng #endif /* __FSP_VPD_H__ */ 146