1*83d290c5STom Rini/* SPDX-License-Identifier: GPL-2.0+ */ 242f8ebfdSBin Meng/* 342f8ebfdSBin Meng * Copyright (C) 2014 Google Inc. 442f8ebfdSBin Meng * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> 542f8ebfdSBin Meng * 642f8ebfdSBin Meng * Modified from coreboot src/soc/intel/baytrail/acpi/xhci.asl 742f8ebfdSBin Meng */ 842f8ebfdSBin Meng 942f8ebfdSBin Meng/* XHCI Controller 0:14.0 */ 1042f8ebfdSBin Meng 1142f8ebfdSBin MengDevice (XHCI) 1242f8ebfdSBin Meng{ 1342f8ebfdSBin Meng Name(_ADR, 0x00140000) 1442f8ebfdSBin Meng 1542f8ebfdSBin Meng /* Power Resources for Wake */ 1642f8ebfdSBin Meng Name(_PRW, Package() { 13, 3 }) 1742f8ebfdSBin Meng 1842f8ebfdSBin Meng /* Highest D state in S3 state */ 1942f8ebfdSBin Meng Name(_S3D, 3) 2042f8ebfdSBin Meng 2142f8ebfdSBin Meng Device (RHUB) 2242f8ebfdSBin Meng { 2342f8ebfdSBin Meng Name(_ADR, 0x00000000) 2442f8ebfdSBin Meng 2542f8ebfdSBin Meng Device (PRT1) { Name(_ADR, 1) } /* USB Port 0 */ 2642f8ebfdSBin Meng Device (PRT2) { Name(_ADR, 2) } /* USB Port 1 */ 2742f8ebfdSBin Meng Device (PRT3) { Name(_ADR, 3) } /* USB Port 2 */ 2842f8ebfdSBin Meng Device (PRT4) { Name(_ADR, 4) } /* USB Port 3 */ 2942f8ebfdSBin Meng } 3042f8ebfdSBin Meng} 31