183d290c5STom Rini// SPDX-License-Identifier: GPL-2.0+ 2683b09d7SBin Meng/* 3683b09d7SBin Meng * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 4683b09d7SBin Meng */ 5683b09d7SBin Meng 6683b09d7SBin Meng/dts-v1/; 7683b09d7SBin Meng 85c564226SBin Meng#include <dt-bindings/interrupt-router/intel-irq.h> 95c564226SBin Meng 105c564226SBin Meng/* ICH9 IRQ router has discrete PIRQ control registers */ 115c564226SBin Meng#undef PIRQE 125c564226SBin Meng#undef PIRQF 135c564226SBin Meng#undef PIRQG 145c564226SBin Meng#undef PIRQH 155c564226SBin Meng#define PIRQE 8 165c564226SBin Meng#define PIRQF 9 175c564226SBin Meng#define PIRQG 10 185c564226SBin Meng#define PIRQH 11 195c564226SBin Meng 20683b09d7SBin Meng/include/ "skeleton.dtsi" 21683b09d7SBin Meng/include/ "serial.dtsi" 22b6ff6ce6SBin Meng/include/ "keyboard.dtsi" 23*b37b7b20SBin Meng/include/ "reset.dtsi" 2493f8a311SBin Meng/include/ "rtc.dtsi" 2580af3984SBin Meng/include/ "tsc_timer.dtsi" 26683b09d7SBin Meng 27683b09d7SBin Meng/ { 28683b09d7SBin Meng model = "QEMU x86 (Q35)"; 29683b09d7SBin Meng compatible = "qemu,x86"; 30683b09d7SBin Meng 31683b09d7SBin Meng config { 32683b09d7SBin Meng silent_console = <0>; 33f2653e8dSBin Meng u-boot,no-apm-finalize; 34683b09d7SBin Meng }; 35683b09d7SBin Meng 36683b09d7SBin Meng chosen { 37683b09d7SBin Meng stdout-path = "/serial"; 38683b09d7SBin Meng }; 39683b09d7SBin Meng 40a8ebf283SBin Meng cpus { 41a8ebf283SBin Meng #address-cells = <1>; 42a8ebf283SBin Meng #size-cells = <0>; 432cffd90fSBin Meng u-boot,dm-pre-reloc; 44a8ebf283SBin Meng 45a8ebf283SBin Meng cpu@0 { 46a8ebf283SBin Meng device_type = "cpu"; 475a694056SMiao Yan compatible = "cpu-qemu"; 482cffd90fSBin Meng u-boot,dm-pre-reloc; 49a8ebf283SBin Meng reg = <0>; 50a8ebf283SBin Meng intel,apic-id = <0>; 51a8ebf283SBin Meng }; 52a8ebf283SBin Meng }; 53a8ebf283SBin Meng 5480af3984SBin Meng tsc-timer { 5580af3984SBin Meng clock-frequency = <1000000000>; 5680af3984SBin Meng }; 5780af3984SBin Meng 58683b09d7SBin Meng pci { 59683b09d7SBin Meng compatible = "pci-x86"; 60683b09d7SBin Meng #address-cells = <3>; 61683b09d7SBin Meng #size-cells = <2>; 62683b09d7SBin Meng u-boot,dm-pre-reloc; 63683b09d7SBin Meng ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000 64683b09d7SBin Meng 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 65683b09d7SBin Meng 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 665c564226SBin Meng 67f2b85ab5SSimon Glass pch@1f,0 { 685c564226SBin Meng reg = <0x0000f800 0 0 0 0>; 69f2b85ab5SSimon Glass compatible = "intel,pch9"; 702cffd90fSBin Meng u-boot,dm-pre-reloc; 71f2b85ab5SSimon Glass 72f2b85ab5SSimon Glass irq-router { 735c564226SBin Meng compatible = "intel,irq-router"; 742cffd90fSBin Meng u-boot,dm-pre-reloc; 755c564226SBin Meng intel,pirq-config = "pci"; 76ce8dd77dSBin Meng intel,actl-8bit; 77ce8dd77dSBin Meng intel,actl-addr = <0x44>; 785c564226SBin Meng intel,pirq-link = <0x60 8>; 795c564226SBin Meng intel,pirq-mask = <0x0e40>; 805c564226SBin Meng intel,pirq-routing = < 815c564226SBin Meng /* e1000 NIC */ 825c564226SBin Meng PCI_BDF(0, 2, 0) INTA PIRQG 835c564226SBin Meng /* ICH9 UHCI */ 845c564226SBin Meng PCI_BDF(0, 29, 0) INTA PIRQA 855c564226SBin Meng PCI_BDF(0, 29, 1) INTB PIRQB 865c564226SBin Meng PCI_BDF(0, 29, 2) INTC PIRQC 875c564226SBin Meng /* ICH9 EHCI */ 885c564226SBin Meng PCI_BDF(0, 29, 7) INTD PIRQD 895c564226SBin Meng /* ICH9 SATA */ 905c564226SBin Meng PCI_BDF(0, 31, 2) INTA PIRQA 915c564226SBin Meng >; 925c564226SBin Meng }; 93683b09d7SBin Meng }; 94f2b85ab5SSimon Glass }; 95683b09d7SBin Meng 96683b09d7SBin Meng}; 97