1b2e02d28SBin Meng /* 2b2e02d28SBin Meng * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 3b2e02d28SBin Meng * 4b2e02d28SBin Meng * SPDX-License-Identifier: GPL-2.0+ 5b2e02d28SBin Meng */ 6b2e02d28SBin Meng 7b2e02d28SBin Meng #include <common.h> 8b2e02d28SBin Meng #include <asm/io.h> 9adfe3b24SBin Meng #include <asm/pci.h> 10b2e02d28SBin Meng #include <asm/post.h> 11*afbf1404SBin Meng #include <asm/arch/device.h> 12*afbf1404SBin Meng #include <asm/arch/irq.h> 131021af4dSSimon Glass #include <asm/fsp/fsp_support.h> 14b2e02d28SBin Meng #include <asm/processor.h> 15b2e02d28SBin Meng 16adfe3b24SBin Meng static void unprotect_spi_flash(void) 17adfe3b24SBin Meng { 18adfe3b24SBin Meng u32 bc; 19adfe3b24SBin Meng 209704f23bSBin Meng bc = x86_pci_read_config32(TNC_LPC, 0xd8); 21adfe3b24SBin Meng bc |= 0x1; /* unprotect the flash */ 229704f23bSBin Meng x86_pci_write_config32(TNC_LPC, 0xd8, bc); 23adfe3b24SBin Meng } 24adfe3b24SBin Meng 25b2e02d28SBin Meng int arch_cpu_init(void) 26b2e02d28SBin Meng { 27adfe3b24SBin Meng struct pci_controller *hose; 28adfe3b24SBin Meng int ret; 29adfe3b24SBin Meng 30b2e02d28SBin Meng post_code(POST_CPU_INIT); 31b2e02d28SBin Meng #ifdef CONFIG_SYS_X86_TSC_TIMER 32b2e02d28SBin Meng timer_set_base(rdtsc()); 33b2e02d28SBin Meng #endif 34b2e02d28SBin Meng 35adfe3b24SBin Meng ret = x86_cpu_init_f(); 36adfe3b24SBin Meng if (ret) 37adfe3b24SBin Meng return ret; 38adfe3b24SBin Meng 39adfe3b24SBin Meng ret = pci_early_init_hose(&hose); 40adfe3b24SBin Meng if (ret) 41adfe3b24SBin Meng return ret; 42adfe3b24SBin Meng 43adfe3b24SBin Meng unprotect_spi_flash(); 44adfe3b24SBin Meng 45adfe3b24SBin Meng return 0; 46b2e02d28SBin Meng } 47*afbf1404SBin Meng 48*afbf1404SBin Meng int arch_misc_init(void) 49*afbf1404SBin Meng { 50*afbf1404SBin Meng pirq_init(); 51*afbf1404SBin Meng 52*afbf1404SBin Meng return 0; 53*afbf1404SBin Meng } 54