1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2faa83232SBin Meng /*
3faa83232SBin Meng * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4faa83232SBin Meng */
5faa83232SBin Meng
6faa83232SBin Meng #include <common.h>
7faa83232SBin Meng #include <asm/arch/device.h>
8faa83232SBin Meng #include <asm/arch/msg_port.h>
95750e5e2SBin Meng #include <asm/arch/quark.h>
10faa83232SBin Meng
msg_port_setup(int op,int port,int reg)11faa83232SBin Meng void msg_port_setup(int op, int port, int reg)
12faa83232SBin Meng {
135750e5e2SBin Meng qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG,
14faa83232SBin Meng (((op) << 24) | ((port) << 16) |
15faa83232SBin Meng (((reg) << 8) & 0xff00) | MSG_BYTE_ENABLE));
16faa83232SBin Meng }
17faa83232SBin Meng
msg_port_read(u8 port,u32 reg)18faa83232SBin Meng u32 msg_port_read(u8 port, u32 reg)
19faa83232SBin Meng {
20faa83232SBin Meng u32 value;
21faa83232SBin Meng
225750e5e2SBin Meng qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
23faa83232SBin Meng reg & 0xffffff00);
24faa83232SBin Meng msg_port_setup(MSG_OP_READ, port, reg);
255750e5e2SBin Meng qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
26faa83232SBin Meng
27faa83232SBin Meng return value;
28faa83232SBin Meng }
29faa83232SBin Meng
msg_port_write(u8 port,u32 reg,u32 value)30faa83232SBin Meng void msg_port_write(u8 port, u32 reg, u32 value)
31faa83232SBin Meng {
325750e5e2SBin Meng qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
335750e5e2SBin Meng qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
34faa83232SBin Meng reg & 0xffffff00);
35faa83232SBin Meng msg_port_setup(MSG_OP_WRITE, port, reg);
36faa83232SBin Meng }
37faa83232SBin Meng
msg_port_alt_read(u8 port,u32 reg)38faa83232SBin Meng u32 msg_port_alt_read(u8 port, u32 reg)
39faa83232SBin Meng {
40faa83232SBin Meng u32 value;
41faa83232SBin Meng
425750e5e2SBin Meng qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
43faa83232SBin Meng reg & 0xffffff00);
44faa83232SBin Meng msg_port_setup(MSG_OP_ALT_READ, port, reg);
455750e5e2SBin Meng qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
46faa83232SBin Meng
47faa83232SBin Meng return value;
48faa83232SBin Meng }
49faa83232SBin Meng
msg_port_alt_write(u8 port,u32 reg,u32 value)50faa83232SBin Meng void msg_port_alt_write(u8 port, u32 reg, u32 value)
51faa83232SBin Meng {
525750e5e2SBin Meng qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
535750e5e2SBin Meng qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
54faa83232SBin Meng reg & 0xffffff00);
55faa83232SBin Meng msg_port_setup(MSG_OP_ALT_WRITE, port, reg);
56faa83232SBin Meng }
57faa83232SBin Meng
msg_port_io_read(u8 port,u32 reg)58faa83232SBin Meng u32 msg_port_io_read(u8 port, u32 reg)
59faa83232SBin Meng {
60faa83232SBin Meng u32 value;
61faa83232SBin Meng
625750e5e2SBin Meng qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
63faa83232SBin Meng reg & 0xffffff00);
64faa83232SBin Meng msg_port_setup(MSG_OP_IO_READ, port, reg);
655750e5e2SBin Meng qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
66faa83232SBin Meng
67faa83232SBin Meng return value;
68faa83232SBin Meng }
69faa83232SBin Meng
msg_port_io_write(u8 port,u32 reg,u32 value)70faa83232SBin Meng void msg_port_io_write(u8 port, u32 reg, u32 value)
71faa83232SBin Meng {
725750e5e2SBin Meng qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
735750e5e2SBin Meng qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
74faa83232SBin Meng reg & 0xffffff00);
75faa83232SBin Meng msg_port_setup(MSG_OP_IO_WRITE, port, reg);
76faa83232SBin Meng }
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