1a65b25d1SBin Meng /* 2a65b25d1SBin Meng * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3a65b25d1SBin Meng * 4a65b25d1SBin Meng * SPDX-License-Identifier: GPL-2.0+ 5a65b25d1SBin Meng */ 6a65b25d1SBin Meng 7a65b25d1SBin Meng #include <common.h> 85c564226SBin Meng #include <asm/irq.h> 9a65b25d1SBin Meng #include <asm/post.h> 10a65b25d1SBin Meng #include <asm/processor.h> 11a65b25d1SBin Meng 12a65b25d1SBin Meng int arch_cpu_init(void) 13a65b25d1SBin Meng { 14a65b25d1SBin Meng int ret; 15a65b25d1SBin Meng 16a65b25d1SBin Meng post_code(POST_CPU_INIT); 17a65b25d1SBin Meng #ifdef CONFIG_SYS_X86_TSC_TIMER 18a65b25d1SBin Meng timer_set_base(rdtsc()); 19a65b25d1SBin Meng #endif 20a65b25d1SBin Meng 21a65b25d1SBin Meng ret = x86_cpu_init_f(); 22a65b25d1SBin Meng if (ret) 23a65b25d1SBin Meng return ret; 24a65b25d1SBin Meng 25a65b25d1SBin Meng return 0; 26a65b25d1SBin Meng } 27a65b25d1SBin Meng 28*eeae5100SSimon Glass #ifndef CONFIG_EFI_STUB 29a65b25d1SBin Meng int print_cpuinfo(void) 30a65b25d1SBin Meng { 31a65b25d1SBin Meng post_code(POST_CPU_INFO); 32a65b25d1SBin Meng return default_print_cpuinfo(); 33a65b25d1SBin Meng } 34*eeae5100SSimon Glass #endif 35a65b25d1SBin Meng 36a65b25d1SBin Meng void reset_cpu(ulong addr) 37a65b25d1SBin Meng { 38a65b25d1SBin Meng /* cold reset */ 39a65b25d1SBin Meng x86_full_reset(); 40a65b25d1SBin Meng } 415c564226SBin Meng 425c564226SBin Meng int arch_misc_init(void) 435c564226SBin Meng { 445c564226SBin Meng pirq_init(); 455c564226SBin Meng 465c564226SBin Meng return 0; 475c564226SBin Meng } 48