1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2a65b25d1SBin Meng /* 3a65b25d1SBin Meng * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 4a65b25d1SBin Meng */ 5a65b25d1SBin Meng 6a65b25d1SBin Meng #include <common.h> 76039200cSBin Meng #include <pci.h> 818686590SMiao Yan #include <qfw.h> 95c564226SBin Meng #include <asm/irq.h> 10a65b25d1SBin Meng #include <asm/post.h> 11a65b25d1SBin Meng #include <asm/processor.h> 1248748595SBin Meng #include <asm/arch/device.h> 1348748595SBin Meng #include <asm/arch/qemu.h> 1448748595SBin Meng 1548748595SBin Meng static bool i440fx; 1648748595SBin Meng 172e82e745SMiao Yan #ifdef CONFIG_QFW 182e82e745SMiao Yan 19331ba7dbSMiao Yan /* on x86, the qfw registers are all IO ports */ 202e82e745SMiao Yan #define FW_CONTROL_PORT 0x510 212e82e745SMiao Yan #define FW_DATA_PORT 0x511 222e82e745SMiao Yan #define FW_DMA_PORT_LOW 0x514 232e82e745SMiao Yan #define FW_DMA_PORT_HIGH 0x518 242e82e745SMiao Yan 252e82e745SMiao Yan static void qemu_x86_fwcfg_read_entry_pio(uint16_t entry, 262e82e745SMiao Yan uint32_t size, void *address) 272e82e745SMiao Yan { 282e82e745SMiao Yan uint32_t i = 0; 292e82e745SMiao Yan uint8_t *data = address; 302e82e745SMiao Yan 312e82e745SMiao Yan /* 322e82e745SMiao Yan * writting FW_CFG_INVALID will cause read operation to resume at 332e82e745SMiao Yan * last offset, otherwise read will start at offset 0 34331ba7dbSMiao Yan * 35331ba7dbSMiao Yan * Note: on platform where the control register is IO port, the 36331ba7dbSMiao Yan * endianness is little endian. 372e82e745SMiao Yan */ 382e82e745SMiao Yan if (entry != FW_CFG_INVALID) 39331ba7dbSMiao Yan outw(cpu_to_le16(entry), FW_CONTROL_PORT); 40331ba7dbSMiao Yan 41331ba7dbSMiao Yan /* the endianness of data register is string-preserving */ 422e82e745SMiao Yan while (size--) 432e82e745SMiao Yan data[i++] = inb(FW_DATA_PORT); 442e82e745SMiao Yan } 452e82e745SMiao Yan 462e82e745SMiao Yan static void qemu_x86_fwcfg_read_entry_dma(struct fw_cfg_dma_access *dma) 472e82e745SMiao Yan { 48331ba7dbSMiao Yan /* the DMA address register is big endian */ 4963767071SBin Meng outl(cpu_to_be32((uintptr_t)dma), FW_DMA_PORT_HIGH); 502e82e745SMiao Yan 512e82e745SMiao Yan while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR) 522e82e745SMiao Yan __asm__ __volatile__ ("pause"); 532e82e745SMiao Yan } 542e82e745SMiao Yan 552e82e745SMiao Yan static struct fw_cfg_arch_ops fwcfg_x86_ops = { 562e82e745SMiao Yan .arch_read_pio = qemu_x86_fwcfg_read_entry_pio, 572e82e745SMiao Yan .arch_read_dma = qemu_x86_fwcfg_read_entry_dma 582e82e745SMiao Yan }; 592e82e745SMiao Yan #endif 602e82e745SMiao Yan 61a3b15a05SMiao Yan static void enable_pm_piix(void) 62a3b15a05SMiao Yan { 63a3b15a05SMiao Yan u8 en; 64a3b15a05SMiao Yan u16 cmd; 65a3b15a05SMiao Yan 66a3b15a05SMiao Yan /* Set the PM I/O base */ 676039200cSBin Meng pci_write_config32(PIIX_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1); 68a3b15a05SMiao Yan 69a3b15a05SMiao Yan /* Enable access to the PM I/O space */ 706039200cSBin Meng pci_read_config16(PIIX_PM, PCI_COMMAND, &cmd); 71a3b15a05SMiao Yan cmd |= PCI_COMMAND_IO; 726039200cSBin Meng pci_write_config16(PIIX_PM, PCI_COMMAND, cmd); 73a3b15a05SMiao Yan 74a3b15a05SMiao Yan /* PM I/O Space Enable (PMIOSE) */ 756039200cSBin Meng pci_read_config8(PIIX_PM, PMREGMISC, &en); 76a3b15a05SMiao Yan en |= PMIOSE; 776039200cSBin Meng pci_write_config8(PIIX_PM, PMREGMISC, en); 78a3b15a05SMiao Yan } 79a3b15a05SMiao Yan 80a3b15a05SMiao Yan static void enable_pm_ich9(void) 81a3b15a05SMiao Yan { 82a3b15a05SMiao Yan /* Set the PM I/O base */ 836039200cSBin Meng pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1); 84a3b15a05SMiao Yan } 85a3b15a05SMiao Yan 8648748595SBin Meng static void qemu_chipset_init(void) 8748748595SBin Meng { 8848748595SBin Meng u16 device, xbcs; 8948748595SBin Meng int pam, i; 9048748595SBin Meng 9148748595SBin Meng /* 9248748595SBin Meng * i440FX and Q35 chipset have different PAM register offset, but with 9348748595SBin Meng * the same bitfield layout. Here we determine the offset based on its 9448748595SBin Meng * PCI device ID. 9548748595SBin Meng */ 966039200cSBin Meng pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID, &device); 9748748595SBin Meng i440fx = (device == PCI_DEVICE_ID_INTEL_82441); 9848748595SBin Meng pam = i440fx ? I440FX_PAM : Q35_PAM; 9948748595SBin Meng 10048748595SBin Meng /* 10148748595SBin Meng * Initialize Programmable Attribute Map (PAM) Registers 10248748595SBin Meng * 10348748595SBin Meng * Configure legacy segments C/D/E/F to system RAM 10448748595SBin Meng */ 10548748595SBin Meng for (i = 0; i < PAM_NUM; i++) 1066039200cSBin Meng pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW); 10748748595SBin Meng 10848748595SBin Meng if (i440fx) { 10948748595SBin Meng /* 11048748595SBin Meng * Enable legacy IDE I/O ports decode 11148748595SBin Meng * 11248748595SBin Meng * Note: QEMU always decode legacy IDE I/O port on PIIX chipset. 11348748595SBin Meng * However Linux ata_piix driver does sanity check on these two 11448748595SBin Meng * registers to see whether legacy ports decode is turned on. 11548748595SBin Meng * This is to make Linux ata_piix driver happy. 11648748595SBin Meng */ 1176039200cSBin Meng pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN); 1186039200cSBin Meng pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN); 11948748595SBin Meng 12048748595SBin Meng /* Enable I/O APIC */ 1216039200cSBin Meng pci_read_config16(PIIX_ISA, XBCS, &xbcs); 12248748595SBin Meng xbcs |= APIC_EN; 1236039200cSBin Meng pci_write_config16(PIIX_ISA, XBCS, xbcs); 124a3b15a05SMiao Yan 125a3b15a05SMiao Yan enable_pm_piix(); 12648748595SBin Meng } else { 12748748595SBin Meng /* Configure PCIe ECAM base address */ 1286039200cSBin Meng pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR, 12948748595SBin Meng CONFIG_PCIE_ECAM_BASE | BAR_EN); 130a3b15a05SMiao Yan 131a3b15a05SMiao Yan enable_pm_ich9(); 13248748595SBin Meng } 133f60df20aSMiao Yan 134fcf5c041SMiao Yan #ifdef CONFIG_QFW 1352e82e745SMiao Yan qemu_fwcfg_init(&fwcfg_x86_ops); 136fcf5c041SMiao Yan #endif 13748748595SBin Meng } 138a65b25d1SBin Meng 139e760feb1SBin Meng #if !CONFIG_IS_ENABLED(SPL_X86_32BIT_INIT) 140a65b25d1SBin Meng int arch_cpu_init(void) 141a65b25d1SBin Meng { 142a65b25d1SBin Meng post_code(POST_CPU_INIT); 143a65b25d1SBin Meng 1440a8547a2SMasahiro Yamada return x86_cpu_init_f(); 145a65b25d1SBin Meng } 146e760feb1SBin Meng #endif 147a65b25d1SBin Meng 148e760feb1SBin Meng #if !CONFIG_IS_ENABLED(EFI_STUB) && \ 149e760feb1SBin Meng !CONFIG_IS_ENABLED(SPL_X86_32BIT_INIT) 15076d1d02fSSimon Glass 15176d1d02fSSimon Glass int checkcpu(void) 15276d1d02fSSimon Glass { 15376d1d02fSSimon Glass return 0; 15476d1d02fSSimon Glass } 15576d1d02fSSimon Glass 156a65b25d1SBin Meng int print_cpuinfo(void) 157a65b25d1SBin Meng { 158a65b25d1SBin Meng post_code(POST_CPU_INFO); 159a65b25d1SBin Meng return default_print_cpuinfo(); 160a65b25d1SBin Meng } 161eeae5100SSimon Glass #endif 162a65b25d1SBin Meng 163a65b25d1SBin Meng void reset_cpu(ulong addr) 164a65b25d1SBin Meng { 165a65b25d1SBin Meng /* cold reset */ 166a65b25d1SBin Meng x86_full_reset(); 167a65b25d1SBin Meng } 1685c564226SBin Meng 16948748595SBin Meng int arch_early_init_r(void) 17048748595SBin Meng { 17148748595SBin Meng qemu_chipset_init(); 17248748595SBin Meng 17348748595SBin Meng return 0; 17448748595SBin Meng } 17548748595SBin Meng 17648748595SBin Meng #ifdef CONFIG_GENERATE_MP_TABLE 17748748595SBin Meng int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) 17848748595SBin Meng { 17948748595SBin Meng u8 irq; 18048748595SBin Meng 18148748595SBin Meng if (i440fx) { 18248748595SBin Meng /* 18348748595SBin Meng * Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not 18448748595SBin Meng * connected to I/O APIC INTPIN#16-19. Instead they are routed 18548748595SBin Meng * to an irq number controled by the PIRQ routing register. 18648748595SBin Meng */ 1876039200cSBin Meng pci_read_config8(PCI_BDF(bus, dev, func), 1886039200cSBin Meng PCI_INTERRUPT_LINE, &irq); 18948748595SBin Meng } else { 19048748595SBin Meng /* 19148748595SBin Meng * ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7. 19248748595SBin Meng * PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11]. 19348748595SBin Meng */ 19448748595SBin Meng irq = pirq < 8 ? pirq + 16 : pirq + 12; 19548748595SBin Meng } 19648748595SBin Meng 19748748595SBin Meng return irq; 19848748595SBin Meng } 19948748595SBin Meng #endif 200