xref: /openbmc/u-boot/arch/x86/cpu/qemu/qemu.c (revision 63767071d977d428264769fe7923da6a59cb166b)
1a65b25d1SBin Meng /*
2a65b25d1SBin Meng  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
3a65b25d1SBin Meng  *
4a65b25d1SBin Meng  * SPDX-License-Identifier:	GPL-2.0+
5a65b25d1SBin Meng  */
6a65b25d1SBin Meng 
7a65b25d1SBin Meng #include <common.h>
86039200cSBin Meng #include <pci.h>
918686590SMiao Yan #include <qfw.h>
105c564226SBin Meng #include <asm/irq.h>
11a65b25d1SBin Meng #include <asm/post.h>
12a65b25d1SBin Meng #include <asm/processor.h>
1348748595SBin Meng #include <asm/arch/device.h>
1448748595SBin Meng #include <asm/arch/qemu.h>
1548748595SBin Meng 
1648748595SBin Meng static bool i440fx;
1748748595SBin Meng 
182e82e745SMiao Yan #ifdef CONFIG_QFW
192e82e745SMiao Yan 
20331ba7dbSMiao Yan /* on x86, the qfw registers are all IO ports */
212e82e745SMiao Yan #define FW_CONTROL_PORT	0x510
222e82e745SMiao Yan #define FW_DATA_PORT		0x511
232e82e745SMiao Yan #define FW_DMA_PORT_LOW	0x514
242e82e745SMiao Yan #define FW_DMA_PORT_HIGH	0x518
252e82e745SMiao Yan 
262e82e745SMiao Yan static void qemu_x86_fwcfg_read_entry_pio(uint16_t entry,
272e82e745SMiao Yan 		uint32_t size, void *address)
282e82e745SMiao Yan {
292e82e745SMiao Yan 	uint32_t i = 0;
302e82e745SMiao Yan 	uint8_t *data = address;
312e82e745SMiao Yan 
322e82e745SMiao Yan 	/*
332e82e745SMiao Yan 	 * writting FW_CFG_INVALID will cause read operation to resume at
342e82e745SMiao Yan 	 * last offset, otherwise read will start at offset 0
35331ba7dbSMiao Yan 	 *
36331ba7dbSMiao Yan 	 * Note: on platform where the control register is IO port, the
37331ba7dbSMiao Yan 	 * endianness is little endian.
382e82e745SMiao Yan 	 */
392e82e745SMiao Yan 	if (entry != FW_CFG_INVALID)
40331ba7dbSMiao Yan 		outw(cpu_to_le16(entry), FW_CONTROL_PORT);
41331ba7dbSMiao Yan 
42331ba7dbSMiao Yan 	/* the endianness of data register is string-preserving */
432e82e745SMiao Yan 	while (size--)
442e82e745SMiao Yan 		data[i++] = inb(FW_DATA_PORT);
452e82e745SMiao Yan }
462e82e745SMiao Yan 
472e82e745SMiao Yan static void qemu_x86_fwcfg_read_entry_dma(struct fw_cfg_dma_access *dma)
482e82e745SMiao Yan {
49331ba7dbSMiao Yan 	/* the DMA address register is big endian */
50*63767071SBin Meng 	outl(cpu_to_be32((uintptr_t)dma), FW_DMA_PORT_HIGH);
512e82e745SMiao Yan 
522e82e745SMiao Yan 	while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR)
532e82e745SMiao Yan 		__asm__ __volatile__ ("pause");
542e82e745SMiao Yan }
552e82e745SMiao Yan 
562e82e745SMiao Yan static struct fw_cfg_arch_ops fwcfg_x86_ops = {
572e82e745SMiao Yan 	.arch_read_pio = qemu_x86_fwcfg_read_entry_pio,
582e82e745SMiao Yan 	.arch_read_dma = qemu_x86_fwcfg_read_entry_dma
592e82e745SMiao Yan };
602e82e745SMiao Yan #endif
612e82e745SMiao Yan 
62a3b15a05SMiao Yan static void enable_pm_piix(void)
63a3b15a05SMiao Yan {
64a3b15a05SMiao Yan 	u8 en;
65a3b15a05SMiao Yan 	u16 cmd;
66a3b15a05SMiao Yan 
67a3b15a05SMiao Yan 	/* Set the PM I/O base */
686039200cSBin Meng 	pci_write_config32(PIIX_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
69a3b15a05SMiao Yan 
70a3b15a05SMiao Yan 	/* Enable access to the PM I/O space */
716039200cSBin Meng 	pci_read_config16(PIIX_PM, PCI_COMMAND, &cmd);
72a3b15a05SMiao Yan 	cmd |= PCI_COMMAND_IO;
736039200cSBin Meng 	pci_write_config16(PIIX_PM, PCI_COMMAND, cmd);
74a3b15a05SMiao Yan 
75a3b15a05SMiao Yan 	/* PM I/O Space Enable (PMIOSE) */
766039200cSBin Meng 	pci_read_config8(PIIX_PM, PMREGMISC, &en);
77a3b15a05SMiao Yan 	en |= PMIOSE;
786039200cSBin Meng 	pci_write_config8(PIIX_PM, PMREGMISC, en);
79a3b15a05SMiao Yan }
80a3b15a05SMiao Yan 
81a3b15a05SMiao Yan static void enable_pm_ich9(void)
82a3b15a05SMiao Yan {
83a3b15a05SMiao Yan 	/* Set the PM I/O base */
846039200cSBin Meng 	pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
85a3b15a05SMiao Yan }
86a3b15a05SMiao Yan 
8748748595SBin Meng static void qemu_chipset_init(void)
8848748595SBin Meng {
8948748595SBin Meng 	u16 device, xbcs;
9048748595SBin Meng 	int pam, i;
9148748595SBin Meng 
9248748595SBin Meng 	/*
9348748595SBin Meng 	 * i440FX and Q35 chipset have different PAM register offset, but with
9448748595SBin Meng 	 * the same bitfield layout. Here we determine the offset based on its
9548748595SBin Meng 	 * PCI device ID.
9648748595SBin Meng 	 */
976039200cSBin Meng 	pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID, &device);
9848748595SBin Meng 	i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
9948748595SBin Meng 	pam = i440fx ? I440FX_PAM : Q35_PAM;
10048748595SBin Meng 
10148748595SBin Meng 	/*
10248748595SBin Meng 	 * Initialize Programmable Attribute Map (PAM) Registers
10348748595SBin Meng 	 *
10448748595SBin Meng 	 * Configure legacy segments C/D/E/F to system RAM
10548748595SBin Meng 	 */
10648748595SBin Meng 	for (i = 0; i < PAM_NUM; i++)
1076039200cSBin Meng 		pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
10848748595SBin Meng 
10948748595SBin Meng 	if (i440fx) {
11048748595SBin Meng 		/*
11148748595SBin Meng 		 * Enable legacy IDE I/O ports decode
11248748595SBin Meng 		 *
11348748595SBin Meng 		 * Note: QEMU always decode legacy IDE I/O port on PIIX chipset.
11448748595SBin Meng 		 * However Linux ata_piix driver does sanity check on these two
11548748595SBin Meng 		 * registers to see whether legacy ports decode is turned on.
11648748595SBin Meng 		 * This is to make Linux ata_piix driver happy.
11748748595SBin Meng 		 */
1186039200cSBin Meng 		pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
1196039200cSBin Meng 		pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);
12048748595SBin Meng 
12148748595SBin Meng 		/* Enable I/O APIC */
1226039200cSBin Meng 		pci_read_config16(PIIX_ISA, XBCS, &xbcs);
12348748595SBin Meng 		xbcs |= APIC_EN;
1246039200cSBin Meng 		pci_write_config16(PIIX_ISA, XBCS, xbcs);
125a3b15a05SMiao Yan 
126a3b15a05SMiao Yan 		enable_pm_piix();
12748748595SBin Meng 	} else {
12848748595SBin Meng 		/* Configure PCIe ECAM base address */
1296039200cSBin Meng 		pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
13048748595SBin Meng 				   CONFIG_PCIE_ECAM_BASE | BAR_EN);
131a3b15a05SMiao Yan 
132a3b15a05SMiao Yan 		enable_pm_ich9();
13348748595SBin Meng 	}
134f60df20aSMiao Yan 
135fcf5c041SMiao Yan #ifdef CONFIG_QFW
1362e82e745SMiao Yan 	qemu_fwcfg_init(&fwcfg_x86_ops);
137fcf5c041SMiao Yan #endif
13848748595SBin Meng }
139a65b25d1SBin Meng 
140e760feb1SBin Meng #if !CONFIG_IS_ENABLED(SPL_X86_32BIT_INIT)
141a65b25d1SBin Meng int arch_cpu_init(void)
142a65b25d1SBin Meng {
143a65b25d1SBin Meng 	post_code(POST_CPU_INIT);
144a65b25d1SBin Meng 
1450a8547a2SMasahiro Yamada 	return x86_cpu_init_f();
146a65b25d1SBin Meng }
147e760feb1SBin Meng #endif
148a65b25d1SBin Meng 
149e760feb1SBin Meng #if !CONFIG_IS_ENABLED(EFI_STUB) && \
150e760feb1SBin Meng 	!CONFIG_IS_ENABLED(SPL_X86_32BIT_INIT)
151a65b25d1SBin Meng int print_cpuinfo(void)
152a65b25d1SBin Meng {
153a65b25d1SBin Meng 	post_code(POST_CPU_INFO);
154a65b25d1SBin Meng 	return default_print_cpuinfo();
155a65b25d1SBin Meng }
156eeae5100SSimon Glass #endif
157a65b25d1SBin Meng 
158a65b25d1SBin Meng void reset_cpu(ulong addr)
159a65b25d1SBin Meng {
160a65b25d1SBin Meng 	/* cold reset */
161a65b25d1SBin Meng 	x86_full_reset();
162a65b25d1SBin Meng }
1635c564226SBin Meng 
16448748595SBin Meng int arch_early_init_r(void)
16548748595SBin Meng {
16648748595SBin Meng 	qemu_chipset_init();
16748748595SBin Meng 
16848748595SBin Meng 	return 0;
16948748595SBin Meng }
17048748595SBin Meng 
17148748595SBin Meng #ifdef CONFIG_GENERATE_MP_TABLE
17248748595SBin Meng int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
17348748595SBin Meng {
17448748595SBin Meng 	u8 irq;
17548748595SBin Meng 
17648748595SBin Meng 	if (i440fx) {
17748748595SBin Meng 		/*
17848748595SBin Meng 		 * Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not
17948748595SBin Meng 		 * connected to I/O APIC INTPIN#16-19. Instead they are routed
18048748595SBin Meng 		 * to an irq number controled by the PIRQ routing register.
18148748595SBin Meng 		 */
1826039200cSBin Meng 		pci_read_config8(PCI_BDF(bus, dev, func),
1836039200cSBin Meng 				 PCI_INTERRUPT_LINE, &irq);
18448748595SBin Meng 	} else {
18548748595SBin Meng 		/*
18648748595SBin Meng 		 * ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7.
18748748595SBin Meng 		 * PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11].
18848748595SBin Meng 		 */
18948748595SBin Meng 		irq = pirq < 8 ? pirq + 16 : pirq + 12;
19048748595SBin Meng 	}
19148748595SBin Meng 
19248748595SBin Meng 	return irq;
19348748595SBin Meng }
19448748595SBin Meng #endif
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