1a65b25d1SBin Meng /* 2a65b25d1SBin Meng * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3a65b25d1SBin Meng * 4a65b25d1SBin Meng * SPDX-License-Identifier: GPL-2.0+ 5a65b25d1SBin Meng */ 6a65b25d1SBin Meng 7a65b25d1SBin Meng #include <common.h> 86039200cSBin Meng #include <pci.h> 9dd6f3abbSTom Rini #include <qemu_fw_cfg.h> 105c564226SBin Meng #include <asm/irq.h> 11a65b25d1SBin Meng #include <asm/post.h> 12a65b25d1SBin Meng #include <asm/processor.h> 1348748595SBin Meng #include <asm/arch/device.h> 1448748595SBin Meng #include <asm/arch/qemu.h> 1548748595SBin Meng 1648748595SBin Meng static bool i440fx; 1748748595SBin Meng 18*2e82e745SMiao Yan #ifdef CONFIG_QFW 19*2e82e745SMiao Yan 20*2e82e745SMiao Yan #define FW_CONTROL_PORT 0x510 21*2e82e745SMiao Yan #define FW_DATA_PORT 0x511 22*2e82e745SMiao Yan #define FW_DMA_PORT_LOW 0x514 23*2e82e745SMiao Yan #define FW_DMA_PORT_HIGH 0x518 24*2e82e745SMiao Yan 25*2e82e745SMiao Yan static void qemu_x86_fwcfg_read_entry_pio(uint16_t entry, 26*2e82e745SMiao Yan uint32_t size, void *address) 27*2e82e745SMiao Yan { 28*2e82e745SMiao Yan uint32_t i = 0; 29*2e82e745SMiao Yan uint8_t *data = address; 30*2e82e745SMiao Yan 31*2e82e745SMiao Yan /* 32*2e82e745SMiao Yan * writting FW_CFG_INVALID will cause read operation to resume at 33*2e82e745SMiao Yan * last offset, otherwise read will start at offset 0 34*2e82e745SMiao Yan */ 35*2e82e745SMiao Yan if (entry != FW_CFG_INVALID) 36*2e82e745SMiao Yan outw(entry, FW_CONTROL_PORT); 37*2e82e745SMiao Yan while (size--) 38*2e82e745SMiao Yan data[i++] = inb(FW_DATA_PORT); 39*2e82e745SMiao Yan } 40*2e82e745SMiao Yan 41*2e82e745SMiao Yan static void qemu_x86_fwcfg_read_entry_dma(struct fw_cfg_dma_access *dma) 42*2e82e745SMiao Yan { 43*2e82e745SMiao Yan outl(cpu_to_be32((uint32_t)dma), FW_DMA_PORT_HIGH); 44*2e82e745SMiao Yan 45*2e82e745SMiao Yan while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR) 46*2e82e745SMiao Yan __asm__ __volatile__ ("pause"); 47*2e82e745SMiao Yan } 48*2e82e745SMiao Yan 49*2e82e745SMiao Yan static struct fw_cfg_arch_ops fwcfg_x86_ops = { 50*2e82e745SMiao Yan .arch_read_pio = qemu_x86_fwcfg_read_entry_pio, 51*2e82e745SMiao Yan .arch_read_dma = qemu_x86_fwcfg_read_entry_dma 52*2e82e745SMiao Yan }; 53*2e82e745SMiao Yan #endif 54*2e82e745SMiao Yan 55a3b15a05SMiao Yan static void enable_pm_piix(void) 56a3b15a05SMiao Yan { 57a3b15a05SMiao Yan u8 en; 58a3b15a05SMiao Yan u16 cmd; 59a3b15a05SMiao Yan 60a3b15a05SMiao Yan /* Set the PM I/O base */ 616039200cSBin Meng pci_write_config32(PIIX_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1); 62a3b15a05SMiao Yan 63a3b15a05SMiao Yan /* Enable access to the PM I/O space */ 646039200cSBin Meng pci_read_config16(PIIX_PM, PCI_COMMAND, &cmd); 65a3b15a05SMiao Yan cmd |= PCI_COMMAND_IO; 666039200cSBin Meng pci_write_config16(PIIX_PM, PCI_COMMAND, cmd); 67a3b15a05SMiao Yan 68a3b15a05SMiao Yan /* PM I/O Space Enable (PMIOSE) */ 696039200cSBin Meng pci_read_config8(PIIX_PM, PMREGMISC, &en); 70a3b15a05SMiao Yan en |= PMIOSE; 716039200cSBin Meng pci_write_config8(PIIX_PM, PMREGMISC, en); 72a3b15a05SMiao Yan } 73a3b15a05SMiao Yan 74a3b15a05SMiao Yan static void enable_pm_ich9(void) 75a3b15a05SMiao Yan { 76a3b15a05SMiao Yan /* Set the PM I/O base */ 776039200cSBin Meng pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1); 78a3b15a05SMiao Yan } 79a3b15a05SMiao Yan 8048748595SBin Meng static void qemu_chipset_init(void) 8148748595SBin Meng { 8248748595SBin Meng u16 device, xbcs; 8348748595SBin Meng int pam, i; 8448748595SBin Meng 8548748595SBin Meng /* 8648748595SBin Meng * i440FX and Q35 chipset have different PAM register offset, but with 8748748595SBin Meng * the same bitfield layout. Here we determine the offset based on its 8848748595SBin Meng * PCI device ID. 8948748595SBin Meng */ 906039200cSBin Meng pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID, &device); 9148748595SBin Meng i440fx = (device == PCI_DEVICE_ID_INTEL_82441); 9248748595SBin Meng pam = i440fx ? I440FX_PAM : Q35_PAM; 9348748595SBin Meng 9448748595SBin Meng /* 9548748595SBin Meng * Initialize Programmable Attribute Map (PAM) Registers 9648748595SBin Meng * 9748748595SBin Meng * Configure legacy segments C/D/E/F to system RAM 9848748595SBin Meng */ 9948748595SBin Meng for (i = 0; i < PAM_NUM; i++) 1006039200cSBin Meng pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW); 10148748595SBin Meng 10248748595SBin Meng if (i440fx) { 10348748595SBin Meng /* 10448748595SBin Meng * Enable legacy IDE I/O ports decode 10548748595SBin Meng * 10648748595SBin Meng * Note: QEMU always decode legacy IDE I/O port on PIIX chipset. 10748748595SBin Meng * However Linux ata_piix driver does sanity check on these two 10848748595SBin Meng * registers to see whether legacy ports decode is turned on. 10948748595SBin Meng * This is to make Linux ata_piix driver happy. 11048748595SBin Meng */ 1116039200cSBin Meng pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN); 1126039200cSBin Meng pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN); 11348748595SBin Meng 11448748595SBin Meng /* Enable I/O APIC */ 1156039200cSBin Meng pci_read_config16(PIIX_ISA, XBCS, &xbcs); 11648748595SBin Meng xbcs |= APIC_EN; 1176039200cSBin Meng pci_write_config16(PIIX_ISA, XBCS, xbcs); 118a3b15a05SMiao Yan 119a3b15a05SMiao Yan enable_pm_piix(); 12048748595SBin Meng } else { 12148748595SBin Meng /* Configure PCIe ECAM base address */ 1226039200cSBin Meng pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR, 12348748595SBin Meng CONFIG_PCIE_ECAM_BASE | BAR_EN); 124a3b15a05SMiao Yan 125a3b15a05SMiao Yan enable_pm_ich9(); 12648748595SBin Meng } 127f60df20aSMiao Yan 128fcf5c041SMiao Yan #ifdef CONFIG_QFW 129*2e82e745SMiao Yan qemu_fwcfg_init(&fwcfg_x86_ops); 130fcf5c041SMiao Yan #endif 13148748595SBin Meng } 132a65b25d1SBin Meng 133a65b25d1SBin Meng int arch_cpu_init(void) 134a65b25d1SBin Meng { 135a65b25d1SBin Meng int ret; 136a65b25d1SBin Meng 137a65b25d1SBin Meng post_code(POST_CPU_INIT); 138a65b25d1SBin Meng 139a65b25d1SBin Meng ret = x86_cpu_init_f(); 140a65b25d1SBin Meng if (ret) 141a65b25d1SBin Meng return ret; 142a65b25d1SBin Meng 143a65b25d1SBin Meng return 0; 144a65b25d1SBin Meng } 145a65b25d1SBin Meng 146eeae5100SSimon Glass #ifndef CONFIG_EFI_STUB 147a65b25d1SBin Meng int print_cpuinfo(void) 148a65b25d1SBin Meng { 149a65b25d1SBin Meng post_code(POST_CPU_INFO); 150a65b25d1SBin Meng return default_print_cpuinfo(); 151a65b25d1SBin Meng } 152eeae5100SSimon Glass #endif 153a65b25d1SBin Meng 154a65b25d1SBin Meng void reset_cpu(ulong addr) 155a65b25d1SBin Meng { 156a65b25d1SBin Meng /* cold reset */ 157a65b25d1SBin Meng x86_full_reset(); 158a65b25d1SBin Meng } 1595c564226SBin Meng 16048748595SBin Meng int arch_early_init_r(void) 16148748595SBin Meng { 16248748595SBin Meng qemu_chipset_init(); 16348748595SBin Meng 16448748595SBin Meng return 0; 16548748595SBin Meng } 16648748595SBin Meng 16748748595SBin Meng #ifdef CONFIG_GENERATE_MP_TABLE 16848748595SBin Meng int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) 16948748595SBin Meng { 17048748595SBin Meng u8 irq; 17148748595SBin Meng 17248748595SBin Meng if (i440fx) { 17348748595SBin Meng /* 17448748595SBin Meng * Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not 17548748595SBin Meng * connected to I/O APIC INTPIN#16-19. Instead they are routed 17648748595SBin Meng * to an irq number controled by the PIRQ routing register. 17748748595SBin Meng */ 1786039200cSBin Meng pci_read_config8(PCI_BDF(bus, dev, func), 1796039200cSBin Meng PCI_INTERRUPT_LINE, &irq); 18048748595SBin Meng } else { 18148748595SBin Meng /* 18248748595SBin Meng * ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7. 18348748595SBin Meng * PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11]. 18448748595SBin Meng */ 18548748595SBin Meng irq = pirq < 8 ? pirq + 16 : pirq + 12; 18648748595SBin Meng } 18748748595SBin Meng 18848748595SBin Meng return irq; 18948748595SBin Meng } 19048748595SBin Meng #endif 191