18ef07571SSimon Glass /* 28ef07571SSimon Glass * Copyright (c) 2011 The Chromium OS Authors. 38ef07571SSimon Glass * (C) Copyright 2010,2011 48ef07571SSimon Glass * Graeme Russ, <graeme.russ@gmail.com> 58ef07571SSimon Glass * 68ef07571SSimon Glass * Portions from Coreboot mainboard/google/link/romstage.c 78ef07571SSimon Glass * Copyright (C) 2007-2010 coresystems GmbH 88ef07571SSimon Glass * Copyright (C) 2011 Google Inc. 98ef07571SSimon Glass * 108ef07571SSimon Glass * SPDX-License-Identifier: GPL-2.0 118ef07571SSimon Glass */ 128ef07571SSimon Glass 138ef07571SSimon Glass #include <common.h> 1465dd74a6SSimon Glass #include <errno.h> 1565dd74a6SSimon Glass #include <fdtdec.h> 1665dd74a6SSimon Glass #include <malloc.h> 17191c008aSSimon Glass #include <net.h> 18191c008aSSimon Glass #include <rtc.h> 19191c008aSSimon Glass #include <spi.h> 20191c008aSSimon Glass #include <spi_flash.h> 2165dd74a6SSimon Glass #include <asm/processor.h> 2265dd74a6SSimon Glass #include <asm/gpio.h> 2365dd74a6SSimon Glass #include <asm/global_data.h> 24aaafcd6cSSimon Glass #include <asm/mtrr.h> 2565dd74a6SSimon Glass #include <asm/pci.h> 2665dd74a6SSimon Glass #include <asm/arch/me.h> 27191c008aSSimon Glass #include <asm/arch/mrccache.h> 2865dd74a6SSimon Glass #include <asm/arch/pei_data.h> 2965dd74a6SSimon Glass #include <asm/arch/pch.h> 3065dd74a6SSimon Glass #include <asm/post.h> 3165dd74a6SSimon Glass #include <asm/arch/sandybridge.h> 3265dd74a6SSimon Glass 3365dd74a6SSimon Glass DECLARE_GLOBAL_DATA_PTR; 3465dd74a6SSimon Glass 35191c008aSSimon Glass #define CMOS_OFFSET_MRC_SEED 152 36191c008aSSimon Glass #define CMOS_OFFSET_MRC_SEED_S3 156 37191c008aSSimon Glass #define CMOS_OFFSET_MRC_SEED_CHK 160 38191c008aSSimon Glass 3965dd74a6SSimon Glass /* 4065dd74a6SSimon Glass * This function looks for the highest region of memory lower than 4GB which 4165dd74a6SSimon Glass * has enough space for U-Boot where U-Boot is aligned on a page boundary. 4265dd74a6SSimon Glass * It overrides the default implementation found elsewhere which simply 4365dd74a6SSimon Glass * picks the end of ram, wherever that may be. The location of the stack, 4465dd74a6SSimon Glass * the relocation address, and how far U-Boot is moved by relocation are 4565dd74a6SSimon Glass * set in the global data structure. 4665dd74a6SSimon Glass */ 4765dd74a6SSimon Glass ulong board_get_usable_ram_top(ulong total_size) 4865dd74a6SSimon Glass { 4965dd74a6SSimon Glass struct memory_info *info = &gd->arch.meminfo; 5065dd74a6SSimon Glass uintptr_t dest_addr = 0; 5165dd74a6SSimon Glass struct memory_area *largest = NULL; 5265dd74a6SSimon Glass int i; 5365dd74a6SSimon Glass 5465dd74a6SSimon Glass /* Find largest area of memory below 4GB */ 5565dd74a6SSimon Glass 5665dd74a6SSimon Glass for (i = 0; i < info->num_areas; i++) { 5765dd74a6SSimon Glass struct memory_area *area = &info->area[i]; 5865dd74a6SSimon Glass 5965dd74a6SSimon Glass if (area->start >= 1ULL << 32) 6065dd74a6SSimon Glass continue; 6165dd74a6SSimon Glass if (!largest || area->size > largest->size) 6265dd74a6SSimon Glass largest = area; 6365dd74a6SSimon Glass } 6465dd74a6SSimon Glass 6565dd74a6SSimon Glass /* If no suitable area was found, return an error. */ 6665dd74a6SSimon Glass assert(largest); 6765dd74a6SSimon Glass if (!largest || largest->size < (2 << 20)) 6865dd74a6SSimon Glass panic("No available memory found for relocation"); 6965dd74a6SSimon Glass 7065dd74a6SSimon Glass dest_addr = largest->start + largest->size; 7165dd74a6SSimon Glass 7265dd74a6SSimon Glass return (ulong)dest_addr; 7365dd74a6SSimon Glass } 7465dd74a6SSimon Glass 7565dd74a6SSimon Glass void dram_init_banksize(void) 7665dd74a6SSimon Glass { 7765dd74a6SSimon Glass struct memory_info *info = &gd->arch.meminfo; 7865dd74a6SSimon Glass int num_banks; 7965dd74a6SSimon Glass int i; 8065dd74a6SSimon Glass 8165dd74a6SSimon Glass for (i = 0, num_banks = 0; i < info->num_areas; i++) { 8265dd74a6SSimon Glass struct memory_area *area = &info->area[i]; 8365dd74a6SSimon Glass 8465dd74a6SSimon Glass if (area->start >= 1ULL << 32) 8565dd74a6SSimon Glass continue; 8665dd74a6SSimon Glass gd->bd->bi_dram[num_banks].start = area->start; 8765dd74a6SSimon Glass gd->bd->bi_dram[num_banks].size = area->size; 8865dd74a6SSimon Glass num_banks++; 8965dd74a6SSimon Glass } 9065dd74a6SSimon Glass } 9165dd74a6SSimon Glass 92191c008aSSimon Glass static int get_mrc_entry(struct spi_flash **sfp, struct fmap_entry *entry) 93191c008aSSimon Glass { 94191c008aSSimon Glass const void *blob = gd->fdt_blob; 95191c008aSSimon Glass int node, spi_node, mrc_node; 96191c008aSSimon Glass int upto; 97191c008aSSimon Glass 98191c008aSSimon Glass /* Find the flash chip within the SPI controller node */ 99191c008aSSimon Glass upto = 0; 100191c008aSSimon Glass spi_node = fdtdec_next_alias(blob, "spi", COMPAT_INTEL_ICH_SPI, &upto); 101191c008aSSimon Glass if (spi_node < 0) 102191c008aSSimon Glass return -ENOENT; 103191c008aSSimon Glass node = fdt_first_subnode(blob, spi_node); 104191c008aSSimon Glass if (node < 0) 105191c008aSSimon Glass return -ECHILD; 106191c008aSSimon Glass 107191c008aSSimon Glass /* Find the place where we put the MRC cache */ 108191c008aSSimon Glass mrc_node = fdt_subnode_offset(blob, node, "rw-mrc-cache"); 109191c008aSSimon Glass if (mrc_node < 0) 110191c008aSSimon Glass return -EPERM; 111191c008aSSimon Glass 112191c008aSSimon Glass if (fdtdec_read_fmap_entry(blob, mrc_node, "rm-mrc-cache", entry)) 113191c008aSSimon Glass return -EINVAL; 114191c008aSSimon Glass 115191c008aSSimon Glass if (sfp) { 116191c008aSSimon Glass *sfp = spi_flash_probe_fdt(blob, node, spi_node); 117191c008aSSimon Glass if (!*sfp) 118191c008aSSimon Glass return -EBADF; 119191c008aSSimon Glass } 120191c008aSSimon Glass 121191c008aSSimon Glass return 0; 122191c008aSSimon Glass } 123191c008aSSimon Glass 124191c008aSSimon Glass static int read_seed_from_cmos(struct pei_data *pei_data) 125191c008aSSimon Glass { 126191c008aSSimon Glass u16 c1, c2, checksum, seed_checksum; 127191c008aSSimon Glass 128191c008aSSimon Glass /* 129191c008aSSimon Glass * Read scrambler seeds from CMOS RAM. We don't want to store them in 130191c008aSSimon Glass * SPI flash since they change on every boot and that would wear down 131191c008aSSimon Glass * the flash too much. So we store these in CMOS and the large MRC 132191c008aSSimon Glass * data in SPI flash. 133191c008aSSimon Glass */ 134191c008aSSimon Glass pei_data->scrambler_seed = rtc_read32(CMOS_OFFSET_MRC_SEED); 135191c008aSSimon Glass debug("Read scrambler seed 0x%08x from CMOS 0x%02x\n", 136191c008aSSimon Glass pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); 137191c008aSSimon Glass 138191c008aSSimon Glass pei_data->scrambler_seed_s3 = rtc_read32(CMOS_OFFSET_MRC_SEED_S3); 139191c008aSSimon Glass debug("Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n", 140191c008aSSimon Glass pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); 141191c008aSSimon Glass 142191c008aSSimon Glass /* Compute seed checksum and compare */ 143191c008aSSimon Glass c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed, 144191c008aSSimon Glass sizeof(u32)); 145191c008aSSimon Glass c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3, 146191c008aSSimon Glass sizeof(u32)); 147191c008aSSimon Glass checksum = add_ip_checksums(sizeof(u32), c1, c2); 148191c008aSSimon Glass 149191c008aSSimon Glass seed_checksum = rtc_read8(CMOS_OFFSET_MRC_SEED_CHK); 150191c008aSSimon Glass seed_checksum |= rtc_read8(CMOS_OFFSET_MRC_SEED_CHK + 1) << 8; 151191c008aSSimon Glass 152191c008aSSimon Glass if (checksum != seed_checksum) { 153191c008aSSimon Glass debug("%s: invalid seed checksum\n", __func__); 154191c008aSSimon Glass pei_data->scrambler_seed = 0; 155191c008aSSimon Glass pei_data->scrambler_seed_s3 = 0; 156191c008aSSimon Glass return -EINVAL; 157191c008aSSimon Glass } 158191c008aSSimon Glass 159191c008aSSimon Glass return 0; 160191c008aSSimon Glass } 161191c008aSSimon Glass 162191c008aSSimon Glass static int prepare_mrc_cache(struct pei_data *pei_data) 163191c008aSSimon Glass { 164191c008aSSimon Glass struct mrc_data_container *mrc_cache; 165191c008aSSimon Glass struct fmap_entry entry; 166191c008aSSimon Glass int ret; 167191c008aSSimon Glass 168191c008aSSimon Glass ret = read_seed_from_cmos(pei_data); 169191c008aSSimon Glass if (ret) 170191c008aSSimon Glass return ret; 171191c008aSSimon Glass ret = get_mrc_entry(NULL, &entry); 172191c008aSSimon Glass if (ret) 173191c008aSSimon Glass return ret; 174191c008aSSimon Glass mrc_cache = mrccache_find_current(&entry); 175191c008aSSimon Glass if (!mrc_cache) 176191c008aSSimon Glass return -ENOENT; 177191c008aSSimon Glass 178191c008aSSimon Glass /* 179191c008aSSimon Glass * TODO(sjg@chromium.org): Skip this for now as it causes boot 180191c008aSSimon Glass * problems 181191c008aSSimon Glass */ 182191c008aSSimon Glass if (0) { 183191c008aSSimon Glass pei_data->mrc_input = mrc_cache->data; 184191c008aSSimon Glass pei_data->mrc_input_len = mrc_cache->data_size; 185191c008aSSimon Glass } 186191c008aSSimon Glass debug("%s: at %p, size %x checksum %04x\n", __func__, 187191c008aSSimon Glass pei_data->mrc_input, pei_data->mrc_input_len, 188191c008aSSimon Glass mrc_cache->checksum); 189191c008aSSimon Glass 190191c008aSSimon Glass return 0; 191191c008aSSimon Glass } 192191c008aSSimon Glass 193191c008aSSimon Glass static int build_mrc_data(struct mrc_data_container **datap) 194191c008aSSimon Glass { 195191c008aSSimon Glass struct mrc_data_container *data; 196191c008aSSimon Glass int orig_len; 197191c008aSSimon Glass int output_len; 198191c008aSSimon Glass 199191c008aSSimon Glass orig_len = gd->arch.mrc_output_len; 200191c008aSSimon Glass output_len = ALIGN(orig_len, 16); 201191c008aSSimon Glass data = malloc(output_len + sizeof(*data)); 202191c008aSSimon Glass if (!data) 203191c008aSSimon Glass return -ENOMEM; 204191c008aSSimon Glass data->signature = MRC_DATA_SIGNATURE; 205191c008aSSimon Glass data->data_size = output_len; 206191c008aSSimon Glass data->reserved = 0; 207191c008aSSimon Glass memcpy(data->data, gd->arch.mrc_output, orig_len); 208191c008aSSimon Glass 209191c008aSSimon Glass /* Zero the unused space in aligned buffer. */ 210191c008aSSimon Glass if (output_len > orig_len) 211191c008aSSimon Glass memset(data->data + orig_len, 0, output_len - orig_len); 212191c008aSSimon Glass 213191c008aSSimon Glass data->checksum = compute_ip_checksum(data->data, output_len); 214191c008aSSimon Glass *datap = data; 215191c008aSSimon Glass 216191c008aSSimon Glass return 0; 217191c008aSSimon Glass } 218191c008aSSimon Glass 219191c008aSSimon Glass static int write_seeds_to_cmos(struct pei_data *pei_data) 220191c008aSSimon Glass { 221191c008aSSimon Glass u16 c1, c2, checksum; 222191c008aSSimon Glass 223191c008aSSimon Glass /* Save the MRC seed values to CMOS */ 224191c008aSSimon Glass rtc_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed); 225191c008aSSimon Glass debug("Save scrambler seed 0x%08x to CMOS 0x%02x\n", 226191c008aSSimon Glass pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); 227191c008aSSimon Glass 228191c008aSSimon Glass rtc_write32(CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3); 229191c008aSSimon Glass debug("Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n", 230191c008aSSimon Glass pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); 231191c008aSSimon Glass 232191c008aSSimon Glass /* Save a simple checksum of the seed values */ 233191c008aSSimon Glass c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed, 234191c008aSSimon Glass sizeof(u32)); 235191c008aSSimon Glass c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3, 236191c008aSSimon Glass sizeof(u32)); 237191c008aSSimon Glass checksum = add_ip_checksums(sizeof(u32), c1, c2); 238191c008aSSimon Glass 239191c008aSSimon Glass rtc_write8(CMOS_OFFSET_MRC_SEED_CHK, checksum & 0xff); 240191c008aSSimon Glass rtc_write8(CMOS_OFFSET_MRC_SEED_CHK + 1, (checksum >> 8) & 0xff); 241191c008aSSimon Glass 242191c008aSSimon Glass return 0; 243191c008aSSimon Glass } 244191c008aSSimon Glass 245191c008aSSimon Glass static int sdram_save_mrc_data(void) 246191c008aSSimon Glass { 247191c008aSSimon Glass struct mrc_data_container *data; 248191c008aSSimon Glass struct fmap_entry entry; 249191c008aSSimon Glass struct spi_flash *sf; 250191c008aSSimon Glass int ret; 251191c008aSSimon Glass 252191c008aSSimon Glass if (!gd->arch.mrc_output_len) 253191c008aSSimon Glass return 0; 254191c008aSSimon Glass debug("Saving %d bytes of MRC output data to SPI flash\n", 255191c008aSSimon Glass gd->arch.mrc_output_len); 256191c008aSSimon Glass 257191c008aSSimon Glass ret = get_mrc_entry(&sf, &entry); 258191c008aSSimon Glass if (ret) 259191c008aSSimon Glass goto err_entry; 260191c008aSSimon Glass ret = build_mrc_data(&data); 261191c008aSSimon Glass if (ret) 262191c008aSSimon Glass goto err_data; 263191c008aSSimon Glass ret = mrccache_update(sf, &entry, data); 264191c008aSSimon Glass if (!ret) 265191c008aSSimon Glass debug("Saved MRC data with checksum %04x\n", data->checksum); 266191c008aSSimon Glass 267191c008aSSimon Glass free(data); 268191c008aSSimon Glass err_data: 269191c008aSSimon Glass spi_flash_free(sf); 270191c008aSSimon Glass err_entry: 271191c008aSSimon Glass if (ret) 272191c008aSSimon Glass debug("%s: Failed: %d\n", __func__, ret); 273191c008aSSimon Glass return ret; 274191c008aSSimon Glass } 275191c008aSSimon Glass 276191c008aSSimon Glass /* Use this hook to save our SDRAM parameters */ 277191c008aSSimon Glass int misc_init_r(void) 278191c008aSSimon Glass { 279191c008aSSimon Glass int ret; 280191c008aSSimon Glass 281191c008aSSimon Glass ret = sdram_save_mrc_data(); 282191c008aSSimon Glass if (ret) 283191c008aSSimon Glass printf("Unable to save MRC data: %d\n", ret); 284191c008aSSimon Glass 285191c008aSSimon Glass return 0; 286191c008aSSimon Glass } 287191c008aSSimon Glass 28865dd74a6SSimon Glass static const char *const ecc_decoder[] = { 28965dd74a6SSimon Glass "inactive", 29065dd74a6SSimon Glass "active on IO", 29165dd74a6SSimon Glass "disabled on IO", 29265dd74a6SSimon Glass "active" 29365dd74a6SSimon Glass }; 29465dd74a6SSimon Glass 29565dd74a6SSimon Glass /* 29665dd74a6SSimon Glass * Dump in the log memory controller configuration as read from the memory 29765dd74a6SSimon Glass * controller registers. 29865dd74a6SSimon Glass */ 29965dd74a6SSimon Glass static void report_memory_config(void) 30065dd74a6SSimon Glass { 30165dd74a6SSimon Glass u32 addr_decoder_common, addr_decode_ch[2]; 30265dd74a6SSimon Glass int i; 30365dd74a6SSimon Glass 30465dd74a6SSimon Glass addr_decoder_common = readl(MCHBAR_REG(0x5000)); 30565dd74a6SSimon Glass addr_decode_ch[0] = readl(MCHBAR_REG(0x5004)); 30665dd74a6SSimon Glass addr_decode_ch[1] = readl(MCHBAR_REG(0x5008)); 30765dd74a6SSimon Glass 30865dd74a6SSimon Glass debug("memcfg DDR3 clock %d MHz\n", 30965dd74a6SSimon Glass (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100); 31065dd74a6SSimon Glass debug("memcfg channel assignment: A: %d, B % d, C % d\n", 31165dd74a6SSimon Glass addr_decoder_common & 3, 31265dd74a6SSimon Glass (addr_decoder_common >> 2) & 3, 31365dd74a6SSimon Glass (addr_decoder_common >> 4) & 3); 31465dd74a6SSimon Glass 31565dd74a6SSimon Glass for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { 31665dd74a6SSimon Glass u32 ch_conf = addr_decode_ch[i]; 31765dd74a6SSimon Glass debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf); 31865dd74a6SSimon Glass debug(" ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); 31965dd74a6SSimon Glass debug(" enhanced interleave mode %s\n", 32065dd74a6SSimon Glass ((ch_conf >> 22) & 1) ? "on" : "off"); 32165dd74a6SSimon Glass debug(" rank interleave %s\n", 32265dd74a6SSimon Glass ((ch_conf >> 21) & 1) ? "on" : "off"); 32365dd74a6SSimon Glass debug(" DIMMA %d MB width x%d %s rank%s\n", 32465dd74a6SSimon Glass ((ch_conf >> 0) & 0xff) * 256, 32565dd74a6SSimon Glass ((ch_conf >> 19) & 1) ? 16 : 8, 32665dd74a6SSimon Glass ((ch_conf >> 17) & 1) ? "dual" : "single", 32765dd74a6SSimon Glass ((ch_conf >> 16) & 1) ? "" : ", selected"); 32865dd74a6SSimon Glass debug(" DIMMB %d MB width x%d %s rank%s\n", 32965dd74a6SSimon Glass ((ch_conf >> 8) & 0xff) * 256, 33065dd74a6SSimon Glass ((ch_conf >> 20) & 1) ? 16 : 8, 33165dd74a6SSimon Glass ((ch_conf >> 18) & 1) ? "dual" : "single", 33265dd74a6SSimon Glass ((ch_conf >> 16) & 1) ? ", selected" : ""); 33365dd74a6SSimon Glass } 33465dd74a6SSimon Glass } 33565dd74a6SSimon Glass 33665dd74a6SSimon Glass static void post_system_agent_init(struct pei_data *pei_data) 33765dd74a6SSimon Glass { 33865dd74a6SSimon Glass /* If PCIe init is skipped, set the PEG clock gating */ 33965dd74a6SSimon Glass if (!pei_data->pcie_init) 34065dd74a6SSimon Glass setbits_le32(MCHBAR_REG(0x7010), 1); 34165dd74a6SSimon Glass } 34265dd74a6SSimon Glass 34365dd74a6SSimon Glass static asmlinkage void console_tx_byte(unsigned char byte) 34465dd74a6SSimon Glass { 34565dd74a6SSimon Glass #ifdef DEBUG 34665dd74a6SSimon Glass putc(byte); 34765dd74a6SSimon Glass #endif 34865dd74a6SSimon Glass } 34965dd74a6SSimon Glass 350191c008aSSimon Glass static int recovery_mode_enabled(void) 351191c008aSSimon Glass { 352191c008aSSimon Glass return false; 353191c008aSSimon Glass } 354191c008aSSimon Glass 35565dd74a6SSimon Glass /** 35665dd74a6SSimon Glass * Find the PEI executable in the ROM and execute it. 35765dd74a6SSimon Glass * 35865dd74a6SSimon Glass * @param pei_data: configuration data for UEFI PEI reference code 35965dd74a6SSimon Glass */ 36065dd74a6SSimon Glass int sdram_initialise(struct pei_data *pei_data) 36165dd74a6SSimon Glass { 36265dd74a6SSimon Glass unsigned version; 36365dd74a6SSimon Glass const char *data; 36465dd74a6SSimon Glass uint16_t done; 36565dd74a6SSimon Glass int ret; 36665dd74a6SSimon Glass 36765dd74a6SSimon Glass report_platform_info(); 36865dd74a6SSimon Glass 36965dd74a6SSimon Glass /* Wait for ME to be ready */ 37065dd74a6SSimon Glass ret = intel_early_me_init(); 37165dd74a6SSimon Glass if (ret) 37265dd74a6SSimon Glass return ret; 37365dd74a6SSimon Glass ret = intel_early_me_uma_size(); 37465dd74a6SSimon Glass if (ret < 0) 37565dd74a6SSimon Glass return ret; 37665dd74a6SSimon Glass 37765dd74a6SSimon Glass debug("Starting UEFI PEI System Agent\n"); 37865dd74a6SSimon Glass 379191c008aSSimon Glass /* 380191c008aSSimon Glass * Do not pass MRC data in for recovery mode boot, 381191c008aSSimon Glass * Always pass it in for S3 resume. 382191c008aSSimon Glass */ 383191c008aSSimon Glass if (!recovery_mode_enabled() || 384191c008aSSimon Glass pei_data->boot_mode == PEI_BOOT_RESUME) { 385191c008aSSimon Glass ret = prepare_mrc_cache(pei_data); 386191c008aSSimon Glass if (ret) 387191c008aSSimon Glass debug("prepare_mrc_cache failed: %d\n", ret); 388191c008aSSimon Glass } 389191c008aSSimon Glass 39065dd74a6SSimon Glass /* If MRC data is not found we cannot continue S3 resume. */ 39165dd74a6SSimon Glass if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) { 39265dd74a6SSimon Glass debug("Giving up in sdram_initialize: No MRC data\n"); 39365dd74a6SSimon Glass outb(0x6, PORT_RESET); 39465dd74a6SSimon Glass cpu_hlt(); 39565dd74a6SSimon Glass } 39665dd74a6SSimon Glass 39765dd74a6SSimon Glass /* Pass console handler in pei_data */ 39865dd74a6SSimon Glass pei_data->tx_byte = console_tx_byte; 39965dd74a6SSimon Glass 40065dd74a6SSimon Glass debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data)); 40165dd74a6SSimon Glass 4028c5224c9SBin Meng data = (char *)CONFIG_X86_MRC_ADDR; 40365dd74a6SSimon Glass if (data) { 40465dd74a6SSimon Glass int rv; 40565dd74a6SSimon Glass int (*func)(struct pei_data *); 40665dd74a6SSimon Glass 40765dd74a6SSimon Glass debug("Calling MRC at %p\n", data); 40865dd74a6SSimon Glass post_code(POST_PRE_MRC); 40965dd74a6SSimon Glass func = (int (*)(struct pei_data *))data; 41065dd74a6SSimon Glass rv = func(pei_data); 41165dd74a6SSimon Glass post_code(POST_MRC); 41265dd74a6SSimon Glass if (rv) { 41365dd74a6SSimon Glass switch (rv) { 41465dd74a6SSimon Glass case -1: 41565dd74a6SSimon Glass printf("PEI version mismatch.\n"); 41665dd74a6SSimon Glass break; 41765dd74a6SSimon Glass case -2: 41865dd74a6SSimon Glass printf("Invalid memory frequency.\n"); 41965dd74a6SSimon Glass break; 42065dd74a6SSimon Glass default: 42165dd74a6SSimon Glass printf("MRC returned %x.\n", rv); 42265dd74a6SSimon Glass } 42365dd74a6SSimon Glass printf("Nonzero MRC return value.\n"); 42465dd74a6SSimon Glass return -EFAULT; 42565dd74a6SSimon Glass } 42665dd74a6SSimon Glass } else { 42765dd74a6SSimon Glass printf("UEFI PEI System Agent not found.\n"); 42865dd74a6SSimon Glass return -ENOSYS; 42965dd74a6SSimon Glass } 43065dd74a6SSimon Glass 43165dd74a6SSimon Glass #if CONFIG_USBDEBUG 43265dd74a6SSimon Glass /* mrc.bin reconfigures USB, so reinit it to have debug */ 43365dd74a6SSimon Glass early_usbdebug_init(); 43465dd74a6SSimon Glass #endif 43565dd74a6SSimon Glass 43665dd74a6SSimon Glass version = readl(MCHBAR_REG(0x5034)); 43765dd74a6SSimon Glass debug("System Agent Version %d.%d.%d Build %d\n", 43865dd74a6SSimon Glass version >> 24 , (version >> 16) & 0xff, 43965dd74a6SSimon Glass (version >> 8) & 0xff, version & 0xff); 440191c008aSSimon Glass debug("MCR output data length %#x at %p\n", pei_data->mrc_output_len, 441191c008aSSimon Glass pei_data->mrc_output); 44265dd74a6SSimon Glass 44365dd74a6SSimon Glass /* 44465dd74a6SSimon Glass * Send ME init done for SandyBridge here. This is done inside the 44565dd74a6SSimon Glass * SystemAgent binary on IvyBridge 44665dd74a6SSimon Glass */ 447*31f57c28SSimon Glass done = x86_pci_read_config32(PCH_DEV, PCI_DEVICE_ID); 44865dd74a6SSimon Glass done &= BASE_REV_MASK; 44965dd74a6SSimon Glass if (BASE_REV_SNB == done) 45065dd74a6SSimon Glass intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); 45165dd74a6SSimon Glass else 45265dd74a6SSimon Glass intel_early_me_status(); 45365dd74a6SSimon Glass 45465dd74a6SSimon Glass post_system_agent_init(pei_data); 45565dd74a6SSimon Glass report_memory_config(); 45665dd74a6SSimon Glass 457191c008aSSimon Glass /* S3 resume: don't save scrambler seed or MRC data */ 458191c008aSSimon Glass if (pei_data->boot_mode != PEI_BOOT_RESUME) { 459191c008aSSimon Glass /* 460191c008aSSimon Glass * This will be copied to SDRAM in reserve_arch(), then written 461191c008aSSimon Glass * to SPI flash in sdram_save_mrc_data() 462191c008aSSimon Glass */ 463191c008aSSimon Glass gd->arch.mrc_output = (char *)pei_data->mrc_output; 464191c008aSSimon Glass gd->arch.mrc_output_len = pei_data->mrc_output_len; 465191c008aSSimon Glass ret = write_seeds_to_cmos(pei_data); 466191c008aSSimon Glass if (ret) 467191c008aSSimon Glass debug("Failed to write seeds to CMOS: %d\n", ret); 468191c008aSSimon Glass } 469191c008aSSimon Glass 470191c008aSSimon Glass return 0; 471191c008aSSimon Glass } 472191c008aSSimon Glass 473191c008aSSimon Glass int reserve_arch(void) 474191c008aSSimon Glass { 475191c008aSSimon Glass u16 checksum; 476191c008aSSimon Glass 477191c008aSSimon Glass checksum = compute_ip_checksum(gd->arch.mrc_output, 478191c008aSSimon Glass gd->arch.mrc_output_len); 479191c008aSSimon Glass debug("Saving %d bytes for MRC output data, checksum %04x\n", 480191c008aSSimon Glass gd->arch.mrc_output_len, checksum); 481191c008aSSimon Glass gd->start_addr_sp -= gd->arch.mrc_output_len; 482191c008aSSimon Glass memcpy((void *)gd->start_addr_sp, gd->arch.mrc_output, 483191c008aSSimon Glass gd->arch.mrc_output_len); 484191c008aSSimon Glass gd->arch.mrc_output = (char *)gd->start_addr_sp; 485191c008aSSimon Glass gd->start_addr_sp &= ~0xf; 486191c008aSSimon Glass 48765dd74a6SSimon Glass return 0; 48865dd74a6SSimon Glass } 48965dd74a6SSimon Glass 49065dd74a6SSimon Glass static int copy_spd(struct pei_data *peid) 49165dd74a6SSimon Glass { 49265dd74a6SSimon Glass const int gpio_vector[] = {41, 42, 43, 10, -1}; 49365dd74a6SSimon Glass int spd_index; 49465dd74a6SSimon Glass const void *blob = gd->fdt_blob; 49565dd74a6SSimon Glass int node, spd_node; 49665dd74a6SSimon Glass int ret, i; 49765dd74a6SSimon Glass 49865dd74a6SSimon Glass for (i = 0; ; i++) { 49965dd74a6SSimon Glass if (gpio_vector[i] == -1) 50065dd74a6SSimon Glass break; 50165dd74a6SSimon Glass ret = gpio_requestf(gpio_vector[i], "spd_id%d", i); 50265dd74a6SSimon Glass if (ret) { 50365dd74a6SSimon Glass debug("%s: Could not request gpio %d\n", __func__, 50465dd74a6SSimon Glass gpio_vector[i]); 50565dd74a6SSimon Glass return ret; 50665dd74a6SSimon Glass } 50765dd74a6SSimon Glass } 50865dd74a6SSimon Glass spd_index = gpio_get_values_as_int(gpio_vector); 50965dd74a6SSimon Glass debug("spd index %d\n", spd_index); 51065dd74a6SSimon Glass node = fdtdec_next_compatible(blob, 0, COMPAT_MEMORY_SPD); 51165dd74a6SSimon Glass if (node < 0) { 51265dd74a6SSimon Glass printf("SPD data not found.\n"); 51365dd74a6SSimon Glass return -ENOENT; 51465dd74a6SSimon Glass } 51565dd74a6SSimon Glass 51665dd74a6SSimon Glass for (spd_node = fdt_first_subnode(blob, node); 51765dd74a6SSimon Glass spd_node > 0; 51865dd74a6SSimon Glass spd_node = fdt_next_subnode(blob, spd_node)) { 51965dd74a6SSimon Glass const char *data; 52065dd74a6SSimon Glass int len; 52165dd74a6SSimon Glass 52265dd74a6SSimon Glass if (fdtdec_get_int(blob, spd_node, "reg", -1) != spd_index) 52365dd74a6SSimon Glass continue; 52465dd74a6SSimon Glass data = fdt_getprop(blob, spd_node, "data", &len); 52565dd74a6SSimon Glass if (len < sizeof(peid->spd_data[0])) { 52665dd74a6SSimon Glass printf("Missing SPD data\n"); 52765dd74a6SSimon Glass return -EINVAL; 52865dd74a6SSimon Glass } 52965dd74a6SSimon Glass 53065dd74a6SSimon Glass debug("Using SDRAM SPD data for '%s'\n", 53165dd74a6SSimon Glass fdt_get_name(blob, spd_node, NULL)); 53265dd74a6SSimon Glass memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0])); 53365dd74a6SSimon Glass break; 53465dd74a6SSimon Glass } 53565dd74a6SSimon Glass 53665dd74a6SSimon Glass if (spd_node < 0) { 53765dd74a6SSimon Glass printf("No SPD data found for index %d\n", spd_index); 53865dd74a6SSimon Glass return -ENOENT; 53965dd74a6SSimon Glass } 54065dd74a6SSimon Glass 54165dd74a6SSimon Glass return 0; 54265dd74a6SSimon Glass } 54365dd74a6SSimon Glass 54465dd74a6SSimon Glass /** 54565dd74a6SSimon Glass * add_memory_area() - Add a new usable memory area to our list 54665dd74a6SSimon Glass * 54765dd74a6SSimon Glass * Note: @start and @end must not span the first 4GB boundary 54865dd74a6SSimon Glass * 54965dd74a6SSimon Glass * @info: Place to store memory info 55065dd74a6SSimon Glass * @start: Start of this memory area 55165dd74a6SSimon Glass * @end: End of this memory area + 1 55265dd74a6SSimon Glass */ 55365dd74a6SSimon Glass static int add_memory_area(struct memory_info *info, 55465dd74a6SSimon Glass uint64_t start, uint64_t end) 55565dd74a6SSimon Glass { 55665dd74a6SSimon Glass struct memory_area *ptr; 55765dd74a6SSimon Glass 55865dd74a6SSimon Glass if (info->num_areas == CONFIG_NR_DRAM_BANKS) 55965dd74a6SSimon Glass return -ENOSPC; 56065dd74a6SSimon Glass 56165dd74a6SSimon Glass ptr = &info->area[info->num_areas]; 56265dd74a6SSimon Glass ptr->start = start; 56365dd74a6SSimon Glass ptr->size = end - start; 56465dd74a6SSimon Glass info->total_memory += ptr->size; 56565dd74a6SSimon Glass if (ptr->start < (1ULL << 32)) 56665dd74a6SSimon Glass info->total_32bit_memory += ptr->size; 56765dd74a6SSimon Glass debug("%d: memory %llx size %llx, total now %llx / %llx\n", 56865dd74a6SSimon Glass info->num_areas, ptr->start, ptr->size, 56965dd74a6SSimon Glass info->total_32bit_memory, info->total_memory); 57065dd74a6SSimon Glass info->num_areas++; 57165dd74a6SSimon Glass 57265dd74a6SSimon Glass return 0; 57365dd74a6SSimon Glass } 57465dd74a6SSimon Glass 57565dd74a6SSimon Glass /** 57665dd74a6SSimon Glass * sdram_find() - Find available memory 57765dd74a6SSimon Glass * 57865dd74a6SSimon Glass * This is a bit complicated since on x86 there are system memory holes all 57965dd74a6SSimon Glass * over the place. We create a list of available memory blocks 58065dd74a6SSimon Glass */ 58165dd74a6SSimon Glass static int sdram_find(pci_dev_t dev) 58265dd74a6SSimon Glass { 58365dd74a6SSimon Glass struct memory_info *info = &gd->arch.meminfo; 58465dd74a6SSimon Glass uint32_t tseg_base, uma_size, tolud; 58565dd74a6SSimon Glass uint64_t tom, me_base, touud; 58665dd74a6SSimon Glass uint64_t uma_memory_base = 0; 58765dd74a6SSimon Glass uint64_t uma_memory_size; 58865dd74a6SSimon Glass unsigned long long tomk; 58965dd74a6SSimon Glass uint16_t ggc; 59065dd74a6SSimon Glass 59165dd74a6SSimon Glass /* Total Memory 2GB example: 59265dd74a6SSimon Glass * 59365dd74a6SSimon Glass * 00000000 0000MB-1992MB 1992MB RAM (writeback) 59465dd74a6SSimon Glass * 7c800000 1992MB-2000MB 8MB TSEG (SMRR) 59565dd74a6SSimon Glass * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached) 59665dd74a6SSimon Glass * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached) 59765dd74a6SSimon Glass * 7f200000 2034MB TOLUD 59865dd74a6SSimon Glass * 7f800000 2040MB MEBASE 59965dd74a6SSimon Glass * 7f800000 2040MB-2048MB 8MB ME UMA (uncached) 60065dd74a6SSimon Glass * 80000000 2048MB TOM 60165dd74a6SSimon Glass * 100000000 4096MB-4102MB 6MB RAM (writeback) 60265dd74a6SSimon Glass * 60365dd74a6SSimon Glass * Total Memory 4GB example: 60465dd74a6SSimon Glass * 60565dd74a6SSimon Glass * 00000000 0000MB-2768MB 2768MB RAM (writeback) 60665dd74a6SSimon Glass * ad000000 2768MB-2776MB 8MB TSEG (SMRR) 60765dd74a6SSimon Glass * ad800000 2776MB-2778MB 2MB GFX GTT (uncached) 60865dd74a6SSimon Glass * ada00000 2778MB-2810MB 32MB GFX UMA (uncached) 60965dd74a6SSimon Glass * afa00000 2810MB TOLUD 61065dd74a6SSimon Glass * ff800000 4088MB MEBASE 61165dd74a6SSimon Glass * ff800000 4088MB-4096MB 8MB ME UMA (uncached) 61265dd74a6SSimon Glass * 100000000 4096MB TOM 61365dd74a6SSimon Glass * 100000000 4096MB-5374MB 1278MB RAM (writeback) 61465dd74a6SSimon Glass * 14fe00000 5368MB TOUUD 61565dd74a6SSimon Glass */ 61665dd74a6SSimon Glass 61765dd74a6SSimon Glass /* Top of Upper Usable DRAM, including remap */ 618*31f57c28SSimon Glass touud = x86_pci_read_config32(dev, TOUUD+4); 61965dd74a6SSimon Glass touud <<= 32; 620*31f57c28SSimon Glass touud |= x86_pci_read_config32(dev, TOUUD); 62165dd74a6SSimon Glass 62265dd74a6SSimon Glass /* Top of Lower Usable DRAM */ 623*31f57c28SSimon Glass tolud = x86_pci_read_config32(dev, TOLUD); 62465dd74a6SSimon Glass 62565dd74a6SSimon Glass /* Top of Memory - does not account for any UMA */ 626*31f57c28SSimon Glass tom = x86_pci_read_config32(dev, 0xa4); 62765dd74a6SSimon Glass tom <<= 32; 628*31f57c28SSimon Glass tom |= x86_pci_read_config32(dev, 0xa0); 62965dd74a6SSimon Glass 63065dd74a6SSimon Glass debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom); 63165dd74a6SSimon Glass 63265dd74a6SSimon Glass /* ME UMA needs excluding if total memory <4GB */ 633*31f57c28SSimon Glass me_base = x86_pci_read_config32(dev, 0x74); 63465dd74a6SSimon Glass me_base <<= 32; 635*31f57c28SSimon Glass me_base |= x86_pci_read_config32(dev, 0x70); 63665dd74a6SSimon Glass 63765dd74a6SSimon Glass debug("MEBASE %llx\n", me_base); 63865dd74a6SSimon Glass 63965dd74a6SSimon Glass /* TODO: Get rid of all this shifting by 10 bits */ 64065dd74a6SSimon Glass tomk = tolud >> 10; 64165dd74a6SSimon Glass if (me_base == tolud) { 64265dd74a6SSimon Glass /* ME is from MEBASE-TOM */ 64365dd74a6SSimon Glass uma_size = (tom - me_base) >> 10; 64465dd74a6SSimon Glass /* Increment TOLUD to account for ME as RAM */ 64565dd74a6SSimon Glass tolud += uma_size << 10; 64665dd74a6SSimon Glass /* UMA starts at old TOLUD */ 64765dd74a6SSimon Glass uma_memory_base = tomk * 1024ULL; 64865dd74a6SSimon Glass uma_memory_size = uma_size * 1024ULL; 64965dd74a6SSimon Glass debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10); 65065dd74a6SSimon Glass } 65165dd74a6SSimon Glass 65265dd74a6SSimon Glass /* Graphics memory comes next */ 653*31f57c28SSimon Glass ggc = x86_pci_read_config16(dev, GGC); 65465dd74a6SSimon Glass if (!(ggc & 2)) { 65565dd74a6SSimon Glass debug("IGD decoded, subtracting "); 65665dd74a6SSimon Glass 65765dd74a6SSimon Glass /* Graphics memory */ 65865dd74a6SSimon Glass uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL; 65965dd74a6SSimon Glass debug("%uM UMA", uma_size >> 10); 66065dd74a6SSimon Glass tomk -= uma_size; 66165dd74a6SSimon Glass uma_memory_base = tomk * 1024ULL; 66265dd74a6SSimon Glass uma_memory_size += uma_size * 1024ULL; 66365dd74a6SSimon Glass 66465dd74a6SSimon Glass /* GTT Graphics Stolen Memory Size (GGMS) */ 66565dd74a6SSimon Glass uma_size = ((ggc >> 8) & 0x3) * 1024ULL; 66665dd74a6SSimon Glass tomk -= uma_size; 66765dd74a6SSimon Glass uma_memory_base = tomk * 1024ULL; 66865dd74a6SSimon Glass uma_memory_size += uma_size * 1024ULL; 66965dd74a6SSimon Glass debug(" and %uM GTT\n", uma_size >> 10); 67065dd74a6SSimon Glass } 67165dd74a6SSimon Glass 67265dd74a6SSimon Glass /* Calculate TSEG size from its base which must be below GTT */ 673*31f57c28SSimon Glass tseg_base = x86_pci_read_config32(dev, 0xb8); 67465dd74a6SSimon Glass uma_size = (uma_memory_base - tseg_base) >> 10; 67565dd74a6SSimon Glass tomk -= uma_size; 67665dd74a6SSimon Glass uma_memory_base = tomk * 1024ULL; 67765dd74a6SSimon Glass uma_memory_size += uma_size * 1024ULL; 67865dd74a6SSimon Glass debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10); 67965dd74a6SSimon Glass 68065dd74a6SSimon Glass debug("Available memory below 4GB: %lluM\n", tomk >> 10); 68165dd74a6SSimon Glass 68265dd74a6SSimon Glass /* Report the memory regions */ 68365dd74a6SSimon Glass add_memory_area(info, 1 << 20, 2 << 28); 68465dd74a6SSimon Glass add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28); 68565dd74a6SSimon Glass add_memory_area(info, (4 << 28) + (2 << 20), tseg_base); 68665dd74a6SSimon Glass add_memory_area(info, 1ULL << 32, touud); 687aaafcd6cSSimon Glass 688aaafcd6cSSimon Glass /* Add MTRRs for memory */ 689aaafcd6cSSimon Glass mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30); 690aaafcd6cSSimon Glass mtrr_add_request(MTRR_TYPE_WRBACK, 2ULL << 30, 512 << 20); 691aaafcd6cSSimon Glass mtrr_add_request(MTRR_TYPE_WRBACK, 0xaULL << 28, 256 << 20); 692aaafcd6cSSimon Glass mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base, 16 << 20); 693aaafcd6cSSimon Glass mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base + (16 << 20), 694aaafcd6cSSimon Glass 32 << 20); 695aaafcd6cSSimon Glass 69665dd74a6SSimon Glass /* 69765dd74a6SSimon Glass * If >= 4GB installed then memory from TOLUD to 4GB 69865dd74a6SSimon Glass * is remapped above TOM, TOUUD will account for both 69965dd74a6SSimon Glass */ 70065dd74a6SSimon Glass if (touud > (1ULL << 32ULL)) { 70165dd74a6SSimon Glass debug("Available memory above 4GB: %lluM\n", 70265dd74a6SSimon Glass (touud >> 20) - 4096); 70365dd74a6SSimon Glass } 70465dd74a6SSimon Glass 70565dd74a6SSimon Glass return 0; 70665dd74a6SSimon Glass } 70765dd74a6SSimon Glass 70865dd74a6SSimon Glass static void rcba_config(void) 70965dd74a6SSimon Glass { 71065dd74a6SSimon Glass /* 71165dd74a6SSimon Glass * GFX INTA -> PIRQA (MSI) 71265dd74a6SSimon Glass * D28IP_P3IP WLAN INTA -> PIRQB 71365dd74a6SSimon Glass * D29IP_E1P EHCI1 INTA -> PIRQD 71465dd74a6SSimon Glass * D26IP_E2P EHCI2 INTA -> PIRQF 71565dd74a6SSimon Glass * D31IP_SIP SATA INTA -> PIRQF (MSI) 71665dd74a6SSimon Glass * D31IP_SMIP SMBUS INTB -> PIRQH 71765dd74a6SSimon Glass * D31IP_TTIP THRT INTC -> PIRQA 71865dd74a6SSimon Glass * D27IP_ZIP HDA INTA -> PIRQA (MSI) 71965dd74a6SSimon Glass * 72065dd74a6SSimon Glass * TRACKPAD -> PIRQE (Edge Triggered) 72165dd74a6SSimon Glass * TOUCHSCREEN -> PIRQG (Edge Triggered) 72265dd74a6SSimon Glass */ 72365dd74a6SSimon Glass 72465dd74a6SSimon Glass /* Device interrupt pin register (board specific) */ 72565dd74a6SSimon Glass writel((INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | 72665dd74a6SSimon Glass (INTB << D31IP_SMIP) | (INTA << D31IP_SIP), RCB_REG(D31IP)); 72765dd74a6SSimon Glass writel(NOINT << D30IP_PIP, RCB_REG(D30IP)); 72865dd74a6SSimon Glass writel(INTA << D29IP_E1P, RCB_REG(D29IP)); 72965dd74a6SSimon Glass writel(INTA << D28IP_P3IP, RCB_REG(D28IP)); 73065dd74a6SSimon Glass writel(INTA << D27IP_ZIP, RCB_REG(D27IP)); 73165dd74a6SSimon Glass writel(INTA << D26IP_E2P, RCB_REG(D26IP)); 73265dd74a6SSimon Glass writel(NOINT << D25IP_LIP, RCB_REG(D25IP)); 73365dd74a6SSimon Glass writel(NOINT << D22IP_MEI1IP, RCB_REG(D22IP)); 73465dd74a6SSimon Glass 73565dd74a6SSimon Glass /* Device interrupt route registers */ 73665dd74a6SSimon Glass writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR)); 73765dd74a6SSimon Glass writel(DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG), RCB_REG(D29IR)); 73865dd74a6SSimon Glass writel(DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE), RCB_REG(D28IR)); 73965dd74a6SSimon Glass writel(DIR_ROUTE(PIRQA, PIRQH, PIRQA, PIRQB), RCB_REG(D27IR)); 74065dd74a6SSimon Glass writel(DIR_ROUTE(PIRQF, PIRQE, PIRQG, PIRQH), RCB_REG(D26IR)); 74165dd74a6SSimon Glass writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D25IR)); 74265dd74a6SSimon Glass writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D22IR)); 74365dd74a6SSimon Glass 74465dd74a6SSimon Glass /* Enable IOAPIC (generic) */ 74565dd74a6SSimon Glass writew(0x0100, RCB_REG(OIC)); 74665dd74a6SSimon Glass /* PCH BWG says to read back the IOAPIC enable register */ 74765dd74a6SSimon Glass (void)readw(RCB_REG(OIC)); 74865dd74a6SSimon Glass 74965dd74a6SSimon Glass /* Disable unused devices (board specific) */ 75065dd74a6SSimon Glass setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS); 75165dd74a6SSimon Glass } 7528ef07571SSimon Glass 7538ef07571SSimon Glass int dram_init(void) 7548ef07571SSimon Glass { 75565dd74a6SSimon Glass struct pei_data pei_data __aligned(8) = { 75665dd74a6SSimon Glass .pei_version = PEI_VERSION, 75765dd74a6SSimon Glass .mchbar = DEFAULT_MCHBAR, 75865dd74a6SSimon Glass .dmibar = DEFAULT_DMIBAR, 75965dd74a6SSimon Glass .epbar = DEFAULT_EPBAR, 7602d934e57SSimon Glass .pciexbar = CONFIG_PCIE_ECAM_BASE, 76165dd74a6SSimon Glass .smbusbar = SMBUS_IO_BASE, 76265dd74a6SSimon Glass .wdbbar = 0x4000000, 76365dd74a6SSimon Glass .wdbsize = 0x1000, 76465dd74a6SSimon Glass .hpet_address = CONFIG_HPET_ADDRESS, 76565dd74a6SSimon Glass .rcba = DEFAULT_RCBABASE, 76665dd74a6SSimon Glass .pmbase = DEFAULT_PMBASE, 76765dd74a6SSimon Glass .gpiobase = DEFAULT_GPIOBASE, 76865dd74a6SSimon Glass .thermalbase = 0xfed08000, 76965dd74a6SSimon Glass .system_type = 0, /* 0 Mobile, 1 Desktop/Server */ 77065dd74a6SSimon Glass .tseg_size = CONFIG_SMM_TSEG_SIZE, 77165dd74a6SSimon Glass .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, 77265dd74a6SSimon Glass .ec_present = 1, 77365dd74a6SSimon Glass .ddr3lv_support = 1, 77465dd74a6SSimon Glass /* 77565dd74a6SSimon Glass * 0 = leave channel enabled 77665dd74a6SSimon Glass * 1 = disable dimm 0 on channel 77765dd74a6SSimon Glass * 2 = disable dimm 1 on channel 77865dd74a6SSimon Glass * 3 = disable dimm 0+1 on channel 77965dd74a6SSimon Glass */ 78065dd74a6SSimon Glass .dimm_channel0_disabled = 2, 78165dd74a6SSimon Glass .dimm_channel1_disabled = 2, 78265dd74a6SSimon Glass .max_ddr3_freq = 1600, 78365dd74a6SSimon Glass .usb_port_config = { 78465dd74a6SSimon Glass /* 78565dd74a6SSimon Glass * Empty and onboard Ports 0-7, set to un-used pin 78665dd74a6SSimon Glass * OC3 78765dd74a6SSimon Glass */ 78865dd74a6SSimon Glass { 0, 3, 0x0000 }, /* P0= Empty */ 78965dd74a6SSimon Glass { 1, 0, 0x0040 }, /* P1= Left USB 1 (OC0) */ 79065dd74a6SSimon Glass { 1, 1, 0x0040 }, /* P2= Left USB 2 (OC1) */ 79165dd74a6SSimon Glass { 1, 3, 0x0040 }, /* P3= SDCARD (no OC) */ 79265dd74a6SSimon Glass { 0, 3, 0x0000 }, /* P4= Empty */ 79365dd74a6SSimon Glass { 1, 3, 0x0040 }, /* P5= WWAN (no OC) */ 79465dd74a6SSimon Glass { 0, 3, 0x0000 }, /* P6= Empty */ 79565dd74a6SSimon Glass { 0, 3, 0x0000 }, /* P7= Empty */ 79665dd74a6SSimon Glass /* 79765dd74a6SSimon Glass * Empty and onboard Ports 8-13, set to un-used pin 79865dd74a6SSimon Glass * OC4 79965dd74a6SSimon Glass */ 80065dd74a6SSimon Glass { 1, 4, 0x0040 }, /* P8= Camera (no OC) */ 80165dd74a6SSimon Glass { 1, 4, 0x0040 }, /* P9= Bluetooth (no OC) */ 80265dd74a6SSimon Glass { 0, 4, 0x0000 }, /* P10= Empty */ 80365dd74a6SSimon Glass { 0, 4, 0x0000 }, /* P11= Empty */ 80465dd74a6SSimon Glass { 0, 4, 0x0000 }, /* P12= Empty */ 80565dd74a6SSimon Glass { 0, 4, 0x0000 }, /* P13= Empty */ 80665dd74a6SSimon Glass }, 80765dd74a6SSimon Glass }; 80865dd74a6SSimon Glass pci_dev_t dev = PCI_BDF(0, 0, 0); 80965dd74a6SSimon Glass int ret; 81065dd74a6SSimon Glass 81165dd74a6SSimon Glass debug("Boot mode %d\n", gd->arch.pei_boot_mode); 81265dd74a6SSimon Glass debug("mcr_input %p\n", pei_data.mrc_input); 81365dd74a6SSimon Glass pei_data.boot_mode = gd->arch.pei_boot_mode; 81465dd74a6SSimon Glass ret = copy_spd(&pei_data); 81565dd74a6SSimon Glass if (!ret) 81665dd74a6SSimon Glass ret = sdram_initialise(&pei_data); 81765dd74a6SSimon Glass if (ret) 81865dd74a6SSimon Glass return ret; 81965dd74a6SSimon Glass 82065dd74a6SSimon Glass rcba_config(); 82165dd74a6SSimon Glass quick_ram_check(); 82265dd74a6SSimon Glass 82365dd74a6SSimon Glass writew(0xCAFE, MCHBAR_REG(SSKPD)); 82465dd74a6SSimon Glass 82565dd74a6SSimon Glass post_code(POST_DRAM); 82665dd74a6SSimon Glass 82765dd74a6SSimon Glass ret = sdram_find(dev); 82865dd74a6SSimon Glass if (ret) 82965dd74a6SSimon Glass return ret; 83065dd74a6SSimon Glass 83165dd74a6SSimon Glass gd->ram_size = gd->arch.meminfo.total_32bit_memory; 8328ef07571SSimon Glass 8338ef07571SSimon Glass return 0; 8348ef07571SSimon Glass } 835