1*4e7a6acaSSimon Glass /* 2*4e7a6acaSSimon Glass * Copyright (C) 2014 Google, Inc 3*4e7a6acaSSimon Glass * 4*4e7a6acaSSimon Glass * SPDX-License-Identifier: GPL-2.0+ 5*4e7a6acaSSimon Glass */ 6*4e7a6acaSSimon Glass 7*4e7a6acaSSimon Glass #include <common.h> 8*4e7a6acaSSimon Glass #include <errno.h> 9*4e7a6acaSSimon Glass #include <fdtdec.h> 10*4e7a6acaSSimon Glass #include <malloc.h> 11*4e7a6acaSSimon Glass #include <asm/lapic.h> 12*4e7a6acaSSimon Glass #include <asm/pci.h> 13*4e7a6acaSSimon Glass #include <asm/arch/bd82x6x.h> 14*4e7a6acaSSimon Glass #include <asm/arch/model_206ax.h> 15*4e7a6acaSSimon Glass #include <asm/arch/pch.h> 16*4e7a6acaSSimon Glass #include <asm/arch/sandybridge.h> 17*4e7a6acaSSimon Glass 18*4e7a6acaSSimon Glass void bd82x6x_pci_init(pci_dev_t dev) 19*4e7a6acaSSimon Glass { 20*4e7a6acaSSimon Glass u16 reg16; 21*4e7a6acaSSimon Glass u8 reg8; 22*4e7a6acaSSimon Glass 23*4e7a6acaSSimon Glass debug("bd82x6x PCI init.\n"); 24*4e7a6acaSSimon Glass /* Enable Bus Master */ 25*4e7a6acaSSimon Glass reg16 = pci_read_config16(dev, PCI_COMMAND); 26*4e7a6acaSSimon Glass reg16 |= PCI_COMMAND_MASTER; 27*4e7a6acaSSimon Glass pci_write_config16(dev, PCI_COMMAND, reg16); 28*4e7a6acaSSimon Glass 29*4e7a6acaSSimon Glass /* This device has no interrupt */ 30*4e7a6acaSSimon Glass pci_write_config8(dev, INTR, 0xff); 31*4e7a6acaSSimon Glass 32*4e7a6acaSSimon Glass /* disable parity error response and SERR */ 33*4e7a6acaSSimon Glass reg16 = pci_read_config16(dev, BCTRL); 34*4e7a6acaSSimon Glass reg16 &= ~(1 << 0); 35*4e7a6acaSSimon Glass reg16 &= ~(1 << 1); 36*4e7a6acaSSimon Glass pci_write_config16(dev, BCTRL, reg16); 37*4e7a6acaSSimon Glass 38*4e7a6acaSSimon Glass /* Master Latency Count must be set to 0x04! */ 39*4e7a6acaSSimon Glass reg8 = pci_read_config8(dev, SMLT); 40*4e7a6acaSSimon Glass reg8 &= 0x07; 41*4e7a6acaSSimon Glass reg8 |= (0x04 << 3); 42*4e7a6acaSSimon Glass pci_write_config8(dev, SMLT, reg8); 43*4e7a6acaSSimon Glass 44*4e7a6acaSSimon Glass /* Will this improve throughput of bus masters? */ 45*4e7a6acaSSimon Glass pci_write_config8(dev, PCI_MIN_GNT, 0x06); 46*4e7a6acaSSimon Glass 47*4e7a6acaSSimon Glass /* Clear errors in status registers */ 48*4e7a6acaSSimon Glass reg16 = pci_read_config16(dev, PSTS); 49*4e7a6acaSSimon Glass /* reg16 |= 0xf900; */ 50*4e7a6acaSSimon Glass pci_write_config16(dev, PSTS, reg16); 51*4e7a6acaSSimon Glass 52*4e7a6acaSSimon Glass reg16 = pci_read_config16(dev, SECSTS); 53*4e7a6acaSSimon Glass /* reg16 |= 0xf900; */ 54*4e7a6acaSSimon Glass pci_write_config16(dev, SECSTS, reg16); 55*4e7a6acaSSimon Glass } 56*4e7a6acaSSimon Glass 57*4e7a6acaSSimon Glass #define PCI_BRIDGE_UPDATE_COMMAND 58*4e7a6acaSSimon Glass void bd82x6x_pci_dev_enable_resources(pci_dev_t dev) 59*4e7a6acaSSimon Glass { 60*4e7a6acaSSimon Glass uint16_t command; 61*4e7a6acaSSimon Glass 62*4e7a6acaSSimon Glass command = pci_read_config16(dev, PCI_COMMAND); 63*4e7a6acaSSimon Glass command |= PCI_COMMAND_IO; 64*4e7a6acaSSimon Glass #ifdef PCI_BRIDGE_UPDATE_COMMAND 65*4e7a6acaSSimon Glass /* 66*4e7a6acaSSimon Glass * If we write to PCI_COMMAND, on some systems this will cause the 67*4e7a6acaSSimon Glass * ROM and APICs to become invisible. 68*4e7a6acaSSimon Glass */ 69*4e7a6acaSSimon Glass debug("%x cmd <- %02x\n", dev, command); 70*4e7a6acaSSimon Glass pci_write_config16(dev, PCI_COMMAND, command); 71*4e7a6acaSSimon Glass #else 72*4e7a6acaSSimon Glass printf("%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command); 73*4e7a6acaSSimon Glass #endif 74*4e7a6acaSSimon Glass } 75*4e7a6acaSSimon Glass 76*4e7a6acaSSimon Glass void bd82x6x_pci_bus_enable_resources(pci_dev_t dev) 77*4e7a6acaSSimon Glass { 78*4e7a6acaSSimon Glass uint16_t ctrl; 79*4e7a6acaSSimon Glass 80*4e7a6acaSSimon Glass ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); 81*4e7a6acaSSimon Glass ctrl |= PCI_COMMAND_IO; 82*4e7a6acaSSimon Glass ctrl |= PCI_BRIDGE_CTL_VGA; 83*4e7a6acaSSimon Glass debug("%x bridge ctrl <- %04x\n", dev, ctrl); 84*4e7a6acaSSimon Glass pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); 85*4e7a6acaSSimon Glass 86*4e7a6acaSSimon Glass bd82x6x_pci_dev_enable_resources(dev); 87*4e7a6acaSSimon Glass } 88*4e7a6acaSSimon Glass 89*4e7a6acaSSimon Glass int bd82x6x_init_pci_devices(void) 90*4e7a6acaSSimon Glass { 91*4e7a6acaSSimon Glass return 0; 92*4e7a6acaSSimon Glass } 93*4e7a6acaSSimon Glass 94*4e7a6acaSSimon Glass int bd82x6x_init(void) 95*4e7a6acaSSimon Glass { 96*4e7a6acaSSimon Glass bd82x6x_pci_init(PCH_DEV); 97*4e7a6acaSSimon Glass 98*4e7a6acaSSimon Glass return 0; 99*4e7a6acaSSimon Glass } 100