1 /* 2 * Copyright (C) 2013, Intel Corporation 3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 4 * Copyright (C) 2015, Kodak Alaris, Inc 5 * 6 * SPDX-License-Identifier: Intel 7 */ 8 9 #include <common.h> 10 #include <fdtdec.h> 11 #include <asm/fsp/fsp_support.h> 12 13 DECLARE_GLOBAL_DATA_PTR; 14 15 /* ALC262 Verb Table - 10EC0262 */ 16 static const u32 verb_table_data13[] = { 17 /* Pin Complex (NID 0x11) */ 18 0x01171cf0, 19 0x01171d11, 20 0x01171e11, 21 0x01171f41, 22 /* Pin Complex (NID 0x12) */ 23 0x01271cf0, 24 0x01271d11, 25 0x01271e11, 26 0x01271f41, 27 /* Pin Complex (NID 0x14) */ 28 0x01471c10, 29 0x01471d40, 30 0x01471e01, 31 0x01471f01, 32 /* Pin Complex (NID 0x15) */ 33 0x01571cf0, 34 0x01571d11, 35 0x01571e11, 36 0x01571f41, 37 /* Pin Complex (NID 0x16) */ 38 0x01671cf0, 39 0x01671d11, 40 0x01671e11, 41 0x01671f41, 42 /* Pin Complex (NID 0x18) */ 43 0x01871c20, 44 0x01871d98, 45 0x01871ea1, 46 0x01871f01, 47 /* Pin Complex (NID 0x19) */ 48 0x01971c21, 49 0x01971d98, 50 0x01971ea1, 51 0x01971f02, 52 /* Pin Complex (NID 0x1A) */ 53 0x01a71c2f, 54 0x01a71d30, 55 0x01a71e81, 56 0x01a71f01, 57 /* Pin Complex */ 58 0x01b71c1f, 59 0x01b71d40, 60 0x01b71e21, 61 0x01b71f02, 62 /* Pin Complex */ 63 0x01c71cf0, 64 0x01c71d11, 65 0x01c71e11, 66 0x01c71f41, 67 /* Pin Complex */ 68 0x01d71c01, 69 0x01d71dc6, 70 0x01d71e14, 71 0x01d71f40, 72 /* Pin Complex */ 73 0x01e71cf0, 74 0x01e71d11, 75 0x01e71e11, 76 0x01e71f41, 77 /* Pin Complex */ 78 0x01f71cf0, 79 0x01f71d11, 80 0x01f71e11, 81 0x01f71f41, 82 }; 83 84 /* 85 * This needs to be in ROM since if we put it in CAR, FSP init loses it when 86 * it drops CAR. 87 * 88 * TODO(sjg@chromium.org): Move to device tree when FSP allows it 89 * 90 * VerbTable: (RealTek ALC262) 91 * Revision ID = 0xFF, support all steps 92 * Codec Verb Table For AZALIA 93 * Codec Address: CAd value (0/1/2) 94 * Codec Vendor: 0x10EC0262 95 */ 96 static const struct azalia_verb_table azalia_verb_table[] = { 97 { 98 { 99 0x10ec0262, 100 0x0000, 101 0xff, 102 0x01, 103 0x000b, 104 0x0002, 105 }, 106 verb_table_data13 107 } 108 }; 109 110 const struct azalia_config azalia_config = { 111 .pme_enable = 1, 112 .docking_supported = 1, 113 .docking_attached = 0, 114 .hdmi_codec_enable = 1, 115 .azalia_v_ci_enable = 1, 116 .rsvdbits = 0, 117 .verb_table_num = 1, 118 .verb_table = azalia_verb_table, 119 .reset_wait_timer_ms = 300 120 }; 121 122 /** 123 * Override the FSP's Azalia configuration data 124 * 125 * @azalia: pointer to be updated to point to a ROM address where Azalia 126 * configuration data is stored 127 */ 128 static void update_fsp_azalia_configs(struct azalia_config **azalia) 129 { 130 *azalia = (struct azalia_config *)&azalia_config; 131 } 132 133 /** 134 * Override the FSP's configuration data. 135 * If the device tree does not specify an integer setting, use the default 136 * provided in Intel's Baytrail_FSP_Gold4.tgz release FSP/BayleyBayFsp.bsf file. 137 */ 138 void update_fsp_configs(struct fsp_config_data *config, 139 struct fspinit_rtbuf *rt_buf) 140 { 141 struct upd_region *fsp_upd = &config->fsp_upd; 142 struct memory_down_data *mem; 143 const void *blob = gd->fdt_blob; 144 int node; 145 146 /* Initialize runtime buffer for fsp_init() */ 147 rt_buf->common.stack_top = config->common.stack_top - 32; 148 rt_buf->common.boot_mode = config->common.boot_mode; 149 rt_buf->common.upd_data = &config->fsp_upd; 150 151 node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP); 152 if (node < 0) { 153 debug("%s: Cannot find FSP node\n", __func__); 154 return; 155 } 156 157 fsp_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node, 158 "fsp,mrc-init-tseg-size", 159 MRC_INIT_TSEG_SIZE_1MB); 160 fsp_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node, 161 "fsp,mrc-init-mmio-size", 162 MRC_INIT_MMIO_SIZE_2048MB); 163 fsp_upd->mrc_init_spd_addr1 = fdtdec_get_int(blob, node, 164 "fsp,mrc-init-spd-addr1", 165 0xa0); 166 fsp_upd->mrc_init_spd_addr2 = fdtdec_get_int(blob, node, 167 "fsp,mrc-init-spd-addr2", 168 0xa2); 169 fsp_upd->emmc_boot_mode = fdtdec_get_int(blob, node, 170 "fsp,emmc-boot-mode", 171 EMMC_BOOT_MODE_EMMC41); 172 fsp_upd->enable_sdio = fdtdec_get_bool(blob, node, "fsp,enable-sdio"); 173 fsp_upd->enable_sdcard = fdtdec_get_bool(blob, node, 174 "fsp,enable-sdcard"); 175 fsp_upd->enable_hsuart0 = fdtdec_get_bool(blob, node, 176 "fsp,enable-hsuart0"); 177 fsp_upd->enable_hsuart1 = fdtdec_get_bool(blob, node, 178 "fsp,enable-hsuart1"); 179 fsp_upd->enable_spi = fdtdec_get_bool(blob, node, "fsp,enable-spi"); 180 fsp_upd->enable_sata = fdtdec_get_bool(blob, node, "fsp,enable-sata"); 181 fsp_upd->sata_mode = fdtdec_get_int(blob, node, "fsp,sata-mode", 182 SATA_MODE_AHCI); 183 fsp_upd->enable_azalia = fdtdec_get_bool(blob, node, 184 "fsp,enable-azalia"); 185 if (fsp_upd->enable_azalia) 186 update_fsp_azalia_configs(&fsp_upd->azalia_cfg_ptr); 187 fsp_upd->enable_xhci = fdtdec_get_bool(blob, node, "fsp,enable-xhci"); 188 fsp_upd->lpe_mode = fdtdec_get_int(blob, node, "fsp,lpe-mode", 189 LPE_MODE_PCI); 190 fsp_upd->lpss_sio_mode = fdtdec_get_int(blob, node, "fsp,lpss-sio-mode", 191 LPSS_SIO_MODE_PCI); 192 fsp_upd->enable_dma0 = fdtdec_get_bool(blob, node, "fsp,enable-dma0"); 193 fsp_upd->enable_dma1 = fdtdec_get_bool(blob, node, "fsp,enable-dma1"); 194 fsp_upd->enable_i2_c0 = fdtdec_get_bool(blob, node, "fsp,enable-i2c0"); 195 fsp_upd->enable_i2_c1 = fdtdec_get_bool(blob, node, "fsp,enable-i2c1"); 196 fsp_upd->enable_i2_c2 = fdtdec_get_bool(blob, node, "fsp,enable-i2c2"); 197 fsp_upd->enable_i2_c3 = fdtdec_get_bool(blob, node, "fsp,enable-i2c3"); 198 fsp_upd->enable_i2_c4 = fdtdec_get_bool(blob, node, "fsp,enable-i2c4"); 199 fsp_upd->enable_i2_c5 = fdtdec_get_bool(blob, node, "fsp,enable-i2c5"); 200 fsp_upd->enable_i2_c6 = fdtdec_get_bool(blob, node, "fsp,enable-i2c6"); 201 fsp_upd->enable_pwm0 = fdtdec_get_bool(blob, node, "fsp,enable-pwm0"); 202 fsp_upd->enable_pwm1 = fdtdec_get_bool(blob, node, "fsp,enable-pwm1"); 203 fsp_upd->enable_hsi = fdtdec_get_bool(blob, node, "fsp,enable-hsi"); 204 fsp_upd->igd_dvmt50_pre_alloc = fdtdec_get_int(blob, node, 205 "fsp,igd-dvmt50-pre-alloc", IGD_DVMT50_PRE_ALLOC_64MB); 206 fsp_upd->aperture_size = fdtdec_get_int(blob, node, "fsp,aperture-size", 207 APERTURE_SIZE_256MB); 208 fsp_upd->gtt_size = fdtdec_get_int(blob, node, "fsp,gtt-size", 209 GTT_SIZE_2MB); 210 fsp_upd->mrc_debug_msg = fdtdec_get_bool(blob, node, 211 "fsp,mrc-debug-msg"); 212 fsp_upd->isp_enable = fdtdec_get_bool(blob, node, "fsp,isp-enable"); 213 fsp_upd->scc_mode = fdtdec_get_int(blob, node, "fsp,scc-mode", 214 SCC_MODE_PCI); 215 fsp_upd->igd_render_standby = fdtdec_get_bool(blob, node, 216 "fsp,igd-render-standby"); 217 fsp_upd->txe_uma_enable = fdtdec_get_bool(blob, node, 218 "fsp,txe-uma-enable"); 219 fsp_upd->os_selection = fdtdec_get_int(blob, node, "fsp,os-selection", 220 OS_SELECTION_LINUX); 221 fsp_upd->emmc45_ddr50_enabled = fdtdec_get_bool(blob, node, 222 "fsp,emmc45-ddr50-enabled"); 223 fsp_upd->emmc45_hs200_enabled = fdtdec_get_bool(blob, node, 224 "fsp,emmc45-hs200-enabled"); 225 fsp_upd->emmc45_retune_timer_value = fdtdec_get_int(blob, node, 226 "fsp,emmc45-retune-timer-value", 8); 227 fsp_upd->enable_igd = fdtdec_get_bool(blob, node, "fsp,enable-igd"); 228 229 mem = &fsp_upd->memory_params; 230 mem->enable_memory_down = fdtdec_get_bool(blob, node, 231 "fsp,enable-memory-down"); 232 if (mem->enable_memory_down) { 233 node = fdtdec_next_compatible(blob, node, 234 COMPAT_INTEL_BAYTRAIL_FSP_MDP); 235 if (node < 0) { 236 debug("%s: Cannot find FSP memory-down-params node\n", 237 __func__); 238 } else { 239 mem->dram_speed = fdtdec_get_int(blob, node, 240 "fsp,dram-speed", 241 DRAM_SPEED_1333MTS); 242 mem->dram_type = fdtdec_get_int(blob, node, 243 "fsp,dram-type", 244 DRAM_TYPE_DDR3L); 245 mem->dimm_0_enable = fdtdec_get_bool(blob, node, 246 "fsp,dimm-0-enable"); 247 mem->dimm_1_enable = fdtdec_get_bool(blob, node, 248 "fsp,dimm-1-enable"); 249 mem->dimm_width = fdtdec_get_int(blob, node, 250 "fsp,dimm-width", 251 DIMM_WIDTH_X8); 252 mem->dimm_density = fdtdec_get_int(blob, node, 253 "fsp,dimm-density", 254 DIMM_DENSITY_2GBIT); 255 mem->dimm_bus_width = fdtdec_get_int(blob, node, 256 "fsp,dimm-bus-width", 257 DIMM_BUS_WIDTH_64BITS); 258 mem->dimm_sides = fdtdec_get_int(blob, node, 259 "fsp,dimm-sides", 260 DIMM_SIDES_1RANKS); 261 mem->dimm_tcl = fdtdec_get_int(blob, node, 262 "fsp,dimm-tcl", 0x09); 263 mem->dimm_trpt_rcd = fdtdec_get_int(blob, node, 264 "fsp,dimm-trpt-rcd", 0x09); 265 mem->dimm_twr = fdtdec_get_int(blob, node, 266 "fsp,dimm-twr", 0x0a); 267 mem->dimm_twtr = fdtdec_get_int(blob, node, 268 "fsp,dimm-twtr", 0x05); 269 mem->dimm_trrd = fdtdec_get_int(blob, node, 270 "fsp,dimm-trrd", 0x04); 271 mem->dimm_trtp = fdtdec_get_int(blob, node, 272 "fsp,dimm-trtp", 0x05); 273 mem->dimm_tfaw = fdtdec_get_int(blob, node, 274 "fsp,dimm-tfaw", 0x14); 275 } 276 } 277 } 278