1819833afSPeter Tyser #ifndef __ASM_SH_CACHE_H 2819833afSPeter Tyser #define __ASM_SH_CACHE_H 3819833afSPeter Tyser 4*7d236662SMasahiro Yamada #if defined(CONFIG_CPU_SH4) 5819833afSPeter Tyser 6819833afSPeter Tyser int cache_control(unsigned int cmd); 7819833afSPeter Tyser 8819833afSPeter Tyser #define L1_CACHE_BYTES 32 92482e3c8SAnton Staaf 10819833afSPeter Tyser struct __large_struct { unsigned long buf[100]; }; 11819833afSPeter Tyser #define __m(x) (*(struct __large_struct *)(x)) 12819833afSPeter Tyser 132482e3c8SAnton Staaf #else 142482e3c8SAnton Staaf 152482e3c8SAnton Staaf /* 162482e3c8SAnton Staaf * 32-bytes is the largest L1 data cache line size for SH the architecture. So 172482e3c8SAnton Staaf * it is a safe default for DMA alignment. 182482e3c8SAnton Staaf */ 192482e3c8SAnton Staaf #define ARCH_DMA_MINALIGN 32 202482e3c8SAnton Staaf 21*7d236662SMasahiro Yamada #endif /* CONFIG_CPU_SH4 */ 22819833afSPeter Tyser 232482e3c8SAnton Staaf /* 242482e3c8SAnton Staaf * Use the L1 data cache line size value for the minimum DMA buffer alignment 252482e3c8SAnton Staaf * on SH. 262482e3c8SAnton Staaf */ 272482e3c8SAnton Staaf #ifndef ARCH_DMA_MINALIGN 282482e3c8SAnton Staaf #define ARCH_DMA_MINALIGN L1_CACHE_BYTES 292482e3c8SAnton Staaf #endif 302482e3c8SAnton Staaf 31819833afSPeter Tyser #endif /* __ASM_SH_CACHE_H */ 32