1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 28f0fec74SPeter Tyser 38f0fec74SPeter Tyser #include <common.h> 48f0fec74SPeter Tyser #include <asm/processor.h> 5754613f7SNobuhiro Iwamatsu #include <asm/system.h> 68f0fec74SPeter Tyser #include <asm/io.h> 78f0fec74SPeter Tyser 88f0fec74SPeter Tyser #define WDT_BASE WTCNT 98f0fec74SPeter Tyser 108f0fec74SPeter Tyser #define WDT_WD (1 << 6) 118f0fec74SPeter Tyser #define WDT_RST_P (0) 128f0fec74SPeter Tyser #define WDT_RST_M (1 << 5) 138f0fec74SPeter Tyser #define WDT_ENABLE (1 << 7) 148f0fec74SPeter Tyser 158f0fec74SPeter Tyser #if defined(CONFIG_WATCHDOG) csr_read(void)168f0fec74SPeter Tyserstatic unsigned char csr_read(void) 178f0fec74SPeter Tyser { 188f0fec74SPeter Tyser return inb(WDT_BASE + 0x04); 198f0fec74SPeter Tyser } 208f0fec74SPeter Tyser cnt_write(unsigned char value)218f0fec74SPeter Tyserstatic void cnt_write(unsigned char value) 228f0fec74SPeter Tyser { 238f0fec74SPeter Tyser outl((unsigned short)value | 0x5A00, WDT_BASE + 0x00); 248f0fec74SPeter Tyser } 258f0fec74SPeter Tyser csr_write(unsigned char value)268f0fec74SPeter Tyserstatic void csr_write(unsigned char value) 278f0fec74SPeter Tyser { 288f0fec74SPeter Tyser outl((unsigned short)value | 0xA500, WDT_BASE + 0x04); 298f0fec74SPeter Tyser } 308f0fec74SPeter Tyser watchdog_reset(void)318f0fec74SPeter Tyservoid watchdog_reset(void) 328f0fec74SPeter Tyser { 338f0fec74SPeter Tyser outl(0x55000000, WDT_BASE + 0x08); 348f0fec74SPeter Tyser } 358f0fec74SPeter Tyser watchdog_init(void)368f0fec74SPeter Tyserint watchdog_init(void) 378f0fec74SPeter Tyser { 388f0fec74SPeter Tyser /* Set overflow time*/ 398f0fec74SPeter Tyser cnt_write(0); 408f0fec74SPeter Tyser /* Power on reset */ 418f0fec74SPeter Tyser csr_write(WDT_WD|WDT_RST_P|WDT_ENABLE); 428f0fec74SPeter Tyser 438f0fec74SPeter Tyser return 0; 448f0fec74SPeter Tyser } 458f0fec74SPeter Tyser watchdog_disable(void)468f0fec74SPeter Tyserint watchdog_disable(void) 478f0fec74SPeter Tyser { 488f0fec74SPeter Tyser csr_write(csr_read() & ~WDT_ENABLE); 498f0fec74SPeter Tyser return 0; 508f0fec74SPeter Tyser } 518f0fec74SPeter Tyser #endif 528f0fec74SPeter Tyser reset_cpu(unsigned long ignored)538f0fec74SPeter Tyservoid reset_cpu(unsigned long ignored) 548f0fec74SPeter Tyser { 55754613f7SNobuhiro Iwamatsu /* Address error with SR.BL=1 first. */ 56754613f7SNobuhiro Iwamatsu trigger_address_error(); 57754613f7SNobuhiro Iwamatsu 588f0fec74SPeter Tyser while (1) 598f0fec74SPeter Tyser ; 608f0fec74SPeter Tyser } 61