1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 26020faf6SRick Chen /* 36020faf6SRick Chen * Copyright (C) 2017 Andes Technology Corporation 46020faf6SRick Chen * Rick Chen, Andes Technology Corporation <rick@andestech.com> 56020faf6SRick Chen */ 66020faf6SRick Chen 76020faf6SRick Chen #ifndef _ASM_RISCV_CACHE_H 86020faf6SRick Chen #define _ASM_RISCV_CACHE_H 96020faf6SRick Chen 106020faf6SRick Chen /* 116020faf6SRick Chen * The current upper bound for RISCV L1 data cache line sizes is 32 bytes. 126020faf6SRick Chen * We use that value for aligning DMA buffers unless the board config has 136020faf6SRick Chen * specified an alternate cache line size. 146020faf6SRick Chen */ 156020faf6SRick Chen #ifdef CONFIG_SYS_CACHELINE_SIZE 166020faf6SRick Chen #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 176020faf6SRick Chen #else 186020faf6SRick Chen #define ARCH_DMA_MINALIGN 32 196020faf6SRick Chen #endif 206020faf6SRick Chen 216020faf6SRick Chen #endif /* _ASM_RISCV_CACHE_H */ 22